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author | liweiwei <liweiwei@iscas.ac.cn> | 2021-12-27 11:34:02 +0800 |
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committer | Weiwei Li <liweiwei@iscas.ac.cn> | 2022-01-30 11:33:03 +0800 |
commit | e205ca655c12df1ae0f6f3105bc8a671b049f161 (patch) | |
tree | 5994a35a1995f8dd55aefdf5db2ae00bb61f44f5 /riscv/decode.h | |
parent | 456913b2c97d55993103594991a7ac73453465f8 (diff) | |
download | riscv-isa-sim-e205ca655c12df1ae0f6f3105bc8a671b049f161.zip riscv-isa-sim-e205ca655c12df1ae0f6f3105bc8a671b049f161.tar.gz riscv-isa-sim-e205ca655c12df1ae0f6f3105bc8a671b049f161.tar.bz2 |
add instructions function for cmo
prefetch.* are hints and share the encoding of ORI with rd = 0. so it can share the implementation of ORI and execute as no-ops
Diffstat (limited to 'riscv/decode.h')
-rw-r--r-- | riscv/decode.h | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/riscv/decode.h b/riscv/decode.h index c2912e4..6f99cf5 100644 --- a/riscv/decode.h +++ b/riscv/decode.h @@ -278,6 +278,15 @@ private: #define require_noover_widen(astart, asize, bstart, bsize) \ require(!is_overlapped_widen(astart, asize, bstart, bsize)) #define require_vm do { if (insn.v_vm() == 0) require(insn.rd() != 0);} while(0); +#define require_envcfg(field) \ + do { \ + if (((STATE.prv != PRV_M) && (m##field == 0)) || \ + ((STATE.prv == PRV_U && !STATE.v) && (s##field == 0))) \ + throw trap_illegal_instruction(insn.bits()); \ + else if (STATE.v && ((h##field == 0) || \ + ((STATE.prv == PRV_U) && (s##field == 0)))) \ + throw trap_virtual_instruction(insn.bits()); \ + } while(0); #define set_fp_exceptions ({ if (softfloat_exceptionFlags) { \ STATE.fflags->write(STATE.fflags->read() | softfloat_exceptionFlags); \ @@ -3038,6 +3047,11 @@ reg_t index[P.VU.vlmax]; \ WRITE_RD(sext_xlen(rd)); \ } +#define DECLARE_XENVCFG_VARS(field) \ + reg_t m##field = get_field(STATE.menvcfg->read(), MENVCFG_##field); \ + reg_t s##field = get_field(STATE.senvcfg->read(), SENVCFG_##field); \ + reg_t h##field = get_field(STATE.henvcfg->read(), HENVCFG_##field) + #define DEBUG_START 0x0 #define DEBUG_END (0x1000 - 1) |