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path: root/target/riscv/cpu.c
AgeCommit message (Expand)AuthorFilesLines
2022-03-03target/riscv: expose zfinx, zdinx, zhinx{min} propertiesWeiwei Li1-0/+5
2022-03-03target/riscv: add cfg properties for zfinx, zdinx and zhinx{min}Weiwei Li1-0/+12
2022-02-16target/riscv: add support for svpbmt extensionWeiwei Li1-0/+1
2022-02-16target/riscv: add support for svinval extensionWeiwei Li1-0/+1
2022-02-16target/riscv: add support for svnapot extensionWeiwei Li1-0/+2
2022-02-16target/riscv: Allow users to force enable AIA CSRs in HARTAnup Patel1-0/+5
2022-02-16target/riscv: Implement AIA local interrupt prioritiesAnup Patel1-0/+19
2022-02-16target/riscv: Allow setting CPU feature from machine/device emulationAnup Patel1-8/+3
2022-02-16target/riscv: Implement hgeie and hgeip CSRsAnup Patel1-20/+47
2022-02-16target/riscv: Implement SGEIP bit in hip and hie CSRsAnup Patel1-1/+2
2022-02-16target/riscv: Add XVentanaCondOps custom extensionPhilipp Tomsich1-0/+3
2022-02-16target/riscv: correct "code should not be reached" for x-rv128Frédéric Pétrot1-2/+1
2022-01-21target/riscv: Set default XLEN for hypervisorLIU Zhiwei1-0/+10
2022-01-21target/riscv: Create current pm fields in envLIU Zhiwei1-0/+1
2022-01-21target/riscv: Use gdb xml according to max mxlenLIU Zhiwei1-5/+3
2022-01-21target/riscv: Extend pc for runtime pc writeLIU Zhiwei1-3/+19
2022-01-21target/riscv: Create xl field in envLIU Zhiwei1-0/+1
2022-01-21target/riscv: rvv-1.0: Allow Zve32f extension to be turned onFrank Chang1-0/+1
2022-01-21target/riscv: rvv-1.0: Add Zve32f extension into RISC-VFrank Chang1-2/+2
2022-01-21target/riscv: rvv-1.0: Allow Zve64f extension to be turned onFrank Chang1-0/+1
2022-01-21target/riscv: rvv-1.0: Add Zve64f extension into RISC-VFrank Chang1-0/+4
2022-01-21target/riscv: Add host cpu typeYifei Jiang1-0/+15
2022-01-21target/riscv: Support setting external interrupt by KVMYifei Jiang1-1/+5
2022-01-21target/riscv: Support start kernel directly by KVMYifei Jiang1-0/+8
2022-01-08target/riscv: setup everything for rv64 to support rv128 executionFrédéric Pétrot1-0/+20
2022-01-08target/riscv: array for the 64 upper bits of 128-bit registersFrédéric Pétrot1-0/+9
2022-01-08target/riscv: Fix position of 'experimental' commentPhilipp Tomsich1-1/+2
2022-01-08target/riscv: Enable the Hypervisor extension by defaultAlistair Francis1-1/+1
2022-01-08target/riscv: Mark the Hypervisor extension as non experimentalAlistair Francis1-1/+1
2021-12-20target/riscv: Enable bitmanip Zb[abcs] instructionsVineet Gupta1-4/+4
2021-12-20target/riscv: gdb: support vector registers for rv64 & rv32Hsiangkai Wang1-0/+2
2021-12-20target/riscv: drop vector 0.7.1 and add 1.0 supportFrank Chang1-8/+8
2021-12-20target/riscv: zfh: add Zfhmin cpu propertyFrank Chang1-0/+1
2021-12-20target/riscv: zfh: add Zfh cpu propertyFrank Chang1-0/+1
2021-11-02target/riscv: Make riscv_cpu_tlb_fill sysemu onlyRichard Henderson1-1/+1
2021-10-28target/riscv: Allow experimental J-ext to be turned onAlexey Baturo1-0/+4
2021-10-28target/riscv: Print new PM CSRs in QEMU logsAlexey Baturo1-0/+7
2021-10-28target/riscv: Support CSRs required for RISC-V PM extension except for the h-...Alexey Baturo1-0/+2
2021-10-22target/riscv: Use riscv_csrrw_debug for cpu_dumpRichard Henderson1-44/+45
2021-10-22target/riscv: Add MXL/SXL/UXL to TB_FLAGSRichard Henderson1-0/+8
2021-10-22target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxlRichard Henderson1-10/+14
2021-10-22target/riscv: Split misa.mxl and misa.extRichard Henderson1-33/+45
2021-10-22target/riscv: Organise the CPU propertiesAlistair Francis1-7/+10
2021-10-22target/riscv: line up all of the registers in the info register dumpTravis Geiselbrecht1-5/+5
2021-10-07target/riscv: Remove RVB (replaced by Zb[abcs])Philipp Tomsich1-26/+0
2021-10-07target/riscv: Add x-zba, x-zbb, x-zbc and x-zbs propertiesPhilipp Tomsich1-0/+4
2021-09-21target/riscv: Expose interrupt pending bits as GPIO linesAlistair Francis1-0/+30
2021-09-21target/riscv: Update the ePMP CSR addressAlistair Francis1-0/+1
2021-09-14target/riscv: Restrict cpu_exec_interrupt() handler to sysemuPhilippe Mathieu-Daudé1-1/+1
2021-09-01target/riscv: Don't wrongly override isa versionLIU Zhiwei1-6/+8
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