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| author | Hsiangkai Wang <kai.wang@sifive.com> | 2021-12-10 15:56:54 +0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2021-12-20 14:53:31 +1000 |
| commit | 719d3561b269d880b2d31e64ed7632407952bad0 (patch) | |
| tree | 982331798264dc5d9883796288c53e230450d688 /target/riscv/cpu.c | |
| parent | d6c4d3f2a693f4520ec72b0bd25be6ec03fee13a (diff) | |
| download | qemu-719d3561b269d880b2d31e64ed7632407952bad0.zip qemu-719d3561b269d880b2d31e64ed7632407952bad0.tar.gz qemu-719d3561b269d880b2d31e64ed7632407952bad0.tar.bz2 | |
target/riscv: gdb: support vector registers for rv64 & rv32
Signed-off-by: Hsiangkai Wang <kai.wang@sifive.com>
Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-69-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv/cpu.c')
| -rw-r--r-- | target/riscv/cpu.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 728092f..9776297 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -675,6 +675,8 @@ static const char *riscv_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname) if (strcmp(xmlname, "riscv-csr.xml") == 0) { return cpu->dyn_csr_xml; + } else if (strcmp(xmlname, "riscv-vector.xml") == 0) { + return cpu->dyn_vreg_xml; } return NULL; |