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| author | Alistair Francis <alistair.francis@wdc.com> | 2022-01-06 07:39:35 +1000 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2022-01-08 15:46:09 +1000 |
| commit | 07cb270a9ac914431577321b0e3e99d79cf56254 (patch) | |
| tree | 2d3892d3383b75f476a54f17cd5f7eb8928a3149 /target/riscv/cpu.c | |
| parent | 6ca7155a8c8d88e5372f0ba337c33e86edbcb295 (diff) | |
| download | qemu-07cb270a9ac914431577321b0e3e99d79cf56254.zip qemu-07cb270a9ac914431577321b0e3e99d79cf56254.tar.gz qemu-07cb270a9ac914431577321b0e3e99d79cf56254.tar.bz2 | |
target/riscv: Enable the Hypervisor extension by default
Let's enable the Hypervisor extension by default. This doesn't affect
named CPUs (such as lowrisc-ibex or sifive-u54) but does enable the
Hypervisor extensions by default for the virt machine.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-Id: <20220105213937.1113508-7-alistair.francis@opensource.wdc.com>
Diffstat (limited to 'target/riscv/cpu.c')
| -rw-r--r-- | target/riscv/cpu.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 9ea67be..29749e8 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -627,7 +627,7 @@ static Property riscv_cpu_properties[] = { DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true), DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true), DEFINE_PROP_BOOL("v", RISCVCPU, cfg.ext_v, false), - DEFINE_PROP_BOOL("h", RISCVCPU, cfg.ext_h, false), + DEFINE_PROP_BOOL("h", RISCVCPU, cfg.ext_h, true), DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true), DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true), |