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| author | Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr> | 2022-01-06 22:00:56 +0100 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2022-01-08 15:46:10 +1000 |
| commit | 2b5470843a6bf10bcc4431d81badec6bfe31f0a7 (patch) | |
| tree | 444313b9acadb43ce1956a288ac5709210e6e9a7 /target/riscv/cpu.c | |
| parent | a1a3aac448cced3161cd0c8a49ac24cd5d58fe14 (diff) | |
| download | qemu-2b5470843a6bf10bcc4431d81badec6bfe31f0a7.zip qemu-2b5470843a6bf10bcc4431d81badec6bfe31f0a7.tar.gz qemu-2b5470843a6bf10bcc4431d81badec6bfe31f0a7.tar.bz2 | |
target/riscv: array for the 64 upper bits of 128-bit registers
The upper 64-bit of the 128-bit registers have now a place inside
the cpu state structure, and are created as globals for future use.
Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220106210108.138226-7-frederic.petrot@univ-grenoble-alpes.fr
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv/cpu.c')
| -rw-r--r-- | target/riscv/cpu.c | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index ce21c1b..1bd4a7c 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -42,6 +42,15 @@ const char * const riscv_int_regnames[] = { "x28/t3", "x29/t4", "x30/t5", "x31/t6" }; +const char * const riscv_int_regnamesh[] = { + "x0h/zeroh", "x1h/rah", "x2h/sph", "x3h/gph", "x4h/tph", "x5h/t0h", + "x6h/t1h", "x7h/t2h", "x8h/s0h", "x9h/s1h", "x10h/a0h", "x11h/a1h", + "x12h/a2h", "x13h/a3h", "x14h/a4h", "x15h/a5h", "x16h/a6h", "x17h/a7h", + "x18h/s2h", "x19h/s3h", "x20h/s4h", "x21h/s5h", "x22h/s6h", "x23h/s7h", + "x24h/s8h", "x25h/s9h", "x26h/s10h", "x27h/s11h", "x28h/t3h", "x29h/t4h", + "x30h/t5h", "x31h/t6h" +}; + const char * const riscv_fpr_regnames[] = { "f0/ft0", "f1/ft1", "f2/ft2", "f3/ft3", "f4/ft4", "f5/ft5", "f6/ft6", "f7/ft7", "f8/fs0", "f9/fs1", "f10/fa0", "f11/fa1", |