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| author | Weiwei Li <liweiwei@iscas.ac.cn> | 2022-02-04 10:26:56 +0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2022-02-16 12:25:52 +1000 |
| commit | 2bacb22446a45b07f542d32b6d760da757233b20 (patch) | |
| tree | c82f0704c3f91cddad65bad7871cbbf424a5308e /target/riscv/cpu.c | |
| parent | b6ecc63c569bb88c0fcadf79fb92bf4b88aefea8 (diff) | |
| download | qemu-2bacb22446a45b07f542d32b6d760da757233b20.zip qemu-2bacb22446a45b07f542d32b6d760da757233b20.tar.gz qemu-2bacb22446a45b07f542d32b6d760da757233b20.tar.bz2 | |
target/riscv: add support for svnapot extension
- add PTE_N bit
- add PTE_N bit check for inner PTE
- update address translation to support 64KiB continuous region (napot_bits = 4)
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220204022658.18097-4-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv/cpu.c')
| -rw-r--r-- | target/riscv/cpu.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 9dce57a..fda99c2 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -774,6 +774,8 @@ static Property riscv_cpu_properties[] = { DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128), DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64), + DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false), + DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, true), DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, true), DEFINE_PROP_BOOL("zbc", RISCVCPU, cfg.ext_zbc, true), |