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| author | Frank Chang <frank.chang@sifive.com> | 2022-01-18 09:45:04 +0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2022-01-21 15:52:56 +1000 |
| commit | b4a99d40276eb5bdfa849cc04344d9a2c4c820ef (patch) | |
| tree | 45290e7550b604833a5a8a001240ef51f6d36c4e /target/riscv/cpu.c | |
| parent | 22599b795c8395fa3e2a90c3b32ca1622035feeb (diff) | |
| download | qemu-b4a99d40276eb5bdfa849cc04344d9a2c4c820ef.zip qemu-b4a99d40276eb5bdfa849cc04344d9a2c4c820ef.tar.gz qemu-b4a99d40276eb5bdfa849cc04344d9a2c4c820ef.tar.bz2 | |
target/riscv: rvv-1.0: Add Zve64f extension into RISC-V
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220118014522.13613-2-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv/cpu.c')
| -rw-r--r-- | target/riscv/cpu.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 32879f1..cdb893d 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -609,6 +609,10 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) } set_vext_version(env, vext_version); } + if (cpu->cfg.ext_zve64f && !cpu->cfg.ext_f) { + error_setg(errp, "Zve64f extension depends upon RVF."); + return; + } if (cpu->cfg.ext_j) { ext |= RVJ; } |