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path: root/opcodes/aarch64-dis.c
AgeCommit message (Expand)AuthorFilesLines
2024-06-25aarch64: Fix sve2p1 dupq instruction operands.Srinath Parvathaneni1-33/+3
2024-06-24aarch64: Add FP8 Neon and SVE multiplication instructionsAndrew Carlotti1-0/+15
2024-06-24gas, aarch64: Add SME2 lutv2 extensionsaurabh.jha@arm.com1-0/+6
2024-05-28gas, aarch64: Add AdvSIMD lut extensionsaurabh.jha@arm.com1-0/+15
2024-04-22aarch64: Fix coding style issue in `aarch64-dis.c'Victor Do Nascimento1-1/+1
2024-04-17aarch64: Remove asserts from operand qualifier decoders [PR31595]Victor Do Nascimento1-18/+80
2024-03-18aarch64: Add support for (M)ADDPT and (M)SUBPT instructionsYury Khrustalev1-0/+17
2024-01-24aarch64: Eliminate unused variable warnings with -DNDEBUGAndrew Carlotti1-2/+3
2024-01-15aarch64: rcpc3: Define address operand fields and inserter/extractorsVictor Do Nascimento1-0/+84
2024-01-15aarch64: Fix tlbi and tlbip instructionsAndrew Carlotti1-0/+1
2024-01-15aarch64: Add SVE2.1 Contiguous load/store instructions.Srinath Parvathaneni1-0/+15
2024-01-15aarch64: Add SVE2.1 dupq, eorqv and extq instructions.Srinath Parvathaneni1-0/+31
2024-01-15aarch64: Add support for FEAT_SVE2p1.Srinath Parvathaneni1-0/+10
2024-01-15aarch64: Add support for FEAT_SME2p1 instructions.Srinath Parvathaneni1-0/+79
2024-01-09aarch64: Add support for 128-bit system register mrrs and msrr insnsVictor Do Nascimento1-0/+1
2024-01-09aarch64: Add support for the SYSP 128-bit system instructionVictor Do Nascimento1-1/+2
2024-01-09aarch64: Add support for xzr register in register pair operandsVictor Do Nascimento1-2/+5
2024-01-04Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2023-09-26aarch64: Restructure feature flag handlingRichard Sandiford1-3/+4
2023-09-08Set insn_type for branch instructions on aarch64Vladimir Mezentsev1-0/+6
2023-08-22aarch64: Improve naming conventions for A and R-profile architectureVictor Do Nascimento1-2/+2
2023-03-30aarch64: Add the SME2 shift instructionsRichard Sandiford1-0/+17
2023-03-30aarch64: Add the SME2 saturating conversion instructionsRichard Sandiford1-0/+4
2023-03-30aarch64: Add the SME2 MLAL and MLSL instructionsRichard Sandiford1-2/+6
2023-03-30aarch64: Add the SME2 maximum/minimum instructionsRichard Sandiford1-0/+7
2023-03-30aarch64: Add the SME2 ADD and SUB instructionsRichard Sandiford1-0/+2
2023-03-30aarch64: Add the SME2 ZT0 instructionsRichard Sandiford1-0/+15
2023-03-30aarch64: Add the SME2 predicate-related instructionsRichard Sandiford1-4/+29
2023-03-30aarch64: Add the SME2 multivector LD1 and ST1 instructionsRichard Sandiford1-1/+20
2023-03-30aarch64: Add the SME2 MOVA instructionsRichard Sandiford1-1/+59
2023-03-30aarch64: Add a _10 suffix to FLD_imm3Richard Sandiford1-2/+2
2023-03-30aarch64: Add support for strided register listsRichard Sandiford1-0/+5
2023-03-30aarch64: Regularise FLD_* suffixesRichard Sandiford1-5/+5
2023-03-30aarch64: Try to report invalid variants against the closest matchRichard Sandiford1-1/+2
2023-03-30aarch64: Rename za_tile_vector to za_indexRichard Sandiford1-17/+17
2023-03-30aarch64: Make SME instructions use F_STRICTRichard Sandiford1-47/+46
2023-01-01Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2022-07-29libopcodes/aarch64: add support for disassembler stylingAndrew Burgess1-32/+215
2022-06-29opcodes/aarch64: split off creation of comment text in disassemblerAndrew Burgess1-2/+13
2022-01-02Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2021-12-03aarch64: Fix uninitialised memoryRichard Sandiford1-1/+1
2021-12-02aarch64: Enforce P/M/E order for MOPS instructionsRichard Sandiford1-4/+23
2021-12-02aarch64: Add support for +mopsRichard Sandiford1-0/+11
2021-11-25Fix building the AArch64 assembler and disassembler when assertions are disab...Nick Clifton1-16/+17
2021-11-17aarch64: [SME] SVE2 instructions added to support SMEPrzemyslaw Wirkus1-0/+43
2021-11-17aarch64: [SME] Add SME mode selection and state access instructionsPrzemyslaw Wirkus1-2/+36
2021-11-17aarch64: [SME] Add LD1x, ST1x, LDR and STR instructionsPrzemyslaw Wirkus1-0/+50
2021-11-17aarch64: [SME] Add MOV and MOVA instructionsPrzemyslaw Wirkus1-0/+58
2021-11-05Missing va_end in aarch64-dis.cAlan Modra1-0/+1
2021-03-31Use bool in opcodesAlan Modra1-212/+212
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