diff options
| author | Richard Sandiford <richard.sandiford@arm.com> | 2023-03-30 11:09:09 +0100 |
|---|---|---|
| committer | Richard Sandiford <richard.sandiford@arm.com> | 2023-03-30 11:09:09 +0100 |
| commit | 1d1060427db0fe4332d5ae34487789d57e873b5c (patch) | |
| tree | a95e9f2fa3a7d34fa20cf206fe563439377e334a /opcodes/aarch64-dis.c | |
| parent | 2f4e3a2c823f7a51630253cd8a8681203b86664b (diff) | |
| download | binutils-1d1060427db0fe4332d5ae34487789d57e873b5c.zip binutils-1d1060427db0fe4332d5ae34487789d57e873b5c.tar.gz binutils-1d1060427db0fe4332d5ae34487789d57e873b5c.tar.bz2 | |
aarch64: Regularise FLD_* suffixes
Some FLD_imm* suffixes used a counting scheme such as FLD_immN,
FLD_immN_2, FLD_immN_3, etc., while others used the lsb as the
suffix. The latter seems more mnemonic, and was a big help
in doing the SME2 work.
Similarly, the _10 suffix on FLD_SME_size_10 was nonobvious.
Presumably it indicated a 2-bit field, but it actually starts
in bit 22.
Diffstat (limited to 'opcodes/aarch64-dis.c')
| -rw-r--r-- | opcodes/aarch64-dis.c | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/opcodes/aarch64-dis.c b/opcodes/aarch64-dis.c index ddbeefa..05e285f 100644 --- a/opcodes/aarch64-dis.c +++ b/opcodes/aarch64-dis.c @@ -335,7 +335,7 @@ aarch64_ext_reglane (const aarch64_operand *self, aarch64_opnd_info *info, unsigned shift; /* index2 for e.g. INS <Vd>.<Ts>[<index1>], <Vn>.<Ts>[<index2>]. */ assert (info->idx == 1); /* Vn */ - aarch64_insn value = extract_field (FLD_imm4, code, 0); + aarch64_insn value = extract_field (FLD_imm4_11, code, 0); /* Depend on AARCH64_OPND_Ed to determine the qualifier. */ info->qualifier = get_expected_qualifier (inst, info->idx); shift = get_logsz (aarch64_get_qualifier_esize (info->qualifier)); @@ -1430,7 +1430,7 @@ aarch64_ext_reg_shifted (const aarch64_operand *self ATTRIBUTE_UNUSED, instructions. */ return false; /* imm6 */ - info->shifter.amount = extract_field (FLD_imm6, code, 0); + info->shifter.amount = extract_field (FLD_imm6_10, code, 0); /* This makes the constraint checking happy. */ info->shifter.operator_present = 1; @@ -1838,7 +1838,7 @@ aarch64_ext_sme_za_list (const aarch64_operand *self, } /* Decode ZA array vector select register (Rv field), optional vector and - memory offset (imm4 field). + memory offset (imm4_11 field). */ bool aarch64_ext_sme_za_array (const aarch64_operand *self, @@ -2669,7 +2669,7 @@ convert_csinc_to_cset (aarch64_inst *inst) /* MOV <Wd>, #<imm> is equivalent to: - MOVZ <Wd>, #<imm16>, LSL #<shift>. + MOVZ <Wd>, #<imm16_5>, LSL #<shift>. A disassembler may output ORR, MOVZ and MOVN as a MOV mnemonic, except when ORR has an immediate that could be generated by a MOVZ or MOVN instruction, @@ -2956,7 +2956,7 @@ aarch64_decode_variant_using_iclass (aarch64_inst *inst) switch (inst->opcode->iclass) { case sme_mov: - variant = extract_fields (inst->value, 0, 2, FLD_SME_Q, FLD_SME_size_10); + variant = extract_fields (inst->value, 0, 2, FLD_SME_Q, FLD_SME_size_22); if (variant >= 4 && variant < 7) return false; if (variant == 7) |