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author | Richard Sandiford <richard.sandiford@arm.com> | 2023-03-30 11:09:04 +0100 |
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committer | Richard Sandiford <richard.sandiford@arm.com> | 2023-03-30 11:09:04 +0100 |
commit | 575c497a4acde05bc67da24ae2d3af5288e8f763 (patch) | |
tree | f474d8adab18ffae18c7c285abedf9dc3111b570 /opcodes/aarch64-dis.c | |
parent | e9e1ddbb9894bc9eb4d091f3406e5f77c78cd7b8 (diff) | |
download | binutils-575c497a4acde05bc67da24ae2d3af5288e8f763.zip binutils-575c497a4acde05bc67da24ae2d3af5288e8f763.tar.gz binutils-575c497a4acde05bc67da24ae2d3af5288e8f763.tar.bz2 |
aarch64: Rename za_tile_vector to za_index
za_tile_vector is also used for indexing ZA as a whole, rather than
just for indexing tiles. The former is more common than the latter
in SME2, so this patch generalises the name to "indexed_za".
The patch also names the associated structure, so that later patches
can reuse it during parsing.
Diffstat (limited to 'opcodes/aarch64-dis.c')
-rw-r--r-- | opcodes/aarch64-dis.c | 34 |
1 files changed, 17 insertions, 17 deletions
diff --git a/opcodes/aarch64-dis.c b/opcodes/aarch64-dis.c index 01881ea..eabcc9e 100644 --- a/opcodes/aarch64-dis.c +++ b/opcodes/aarch64-dis.c @@ -1786,34 +1786,34 @@ aarch64_ext_sme_za_hv_tiles (const aarch64_operand *self, /* Deduce qualifier encoded in size and Q fields. */ if (fld_size == 0) { - info->za_tile_vector.regno = 0; - info->za_tile_vector.index.imm = fld_zan_imm; + info->indexed_za.regno = 0; + info->indexed_za.index.imm = fld_zan_imm; } else if (fld_size == 1) { - info->za_tile_vector.regno = fld_zan_imm >> 3; - info->za_tile_vector.index.imm = fld_zan_imm & 0x07; + info->indexed_za.regno = fld_zan_imm >> 3; + info->indexed_za.index.imm = fld_zan_imm & 0x07; } else if (fld_size == 2) { - info->za_tile_vector.regno = fld_zan_imm >> 2; - info->za_tile_vector.index.imm = fld_zan_imm & 0x03; + info->indexed_za.regno = fld_zan_imm >> 2; + info->indexed_za.index.imm = fld_zan_imm & 0x03; } else if (fld_size == 3 && fld_q == 0) { - info->za_tile_vector.regno = fld_zan_imm >> 1; - info->za_tile_vector.index.imm = fld_zan_imm & 0x01; + info->indexed_za.regno = fld_zan_imm >> 1; + info->indexed_za.index.imm = fld_zan_imm & 0x01; } else if (fld_size == 3 && fld_q == 1) { - info->za_tile_vector.regno = fld_zan_imm; - info->za_tile_vector.index.imm = 0; + info->indexed_za.regno = fld_zan_imm; + info->indexed_za.index.imm = 0; } else return false; - info->za_tile_vector.index.regno = fld_rv + 12; - info->za_tile_vector.v = fld_v; + info->indexed_za.index.regno = fld_rv + 12; + info->indexed_za.v = fld_v; return true; } @@ -1847,8 +1847,8 @@ aarch64_ext_sme_za_array (const aarch64_operand *self, { int regno = extract_field (self->fields[0], code, 0) + 12; int imm = extract_field (self->fields[1], code, 0); - info->za_tile_vector.index.regno = regno; - info->za_tile_vector.index.imm = imm; + info->indexed_za.index.regno = regno; + info->indexed_za.index.imm = imm; return true; } @@ -1902,8 +1902,8 @@ aarch64_ext_sme_pred_reg_with_index (const aarch64_operand *self, aarch64_insn fld_tszl = extract_field (self->fields[4], code, 0); int imm; - info->za_tile_vector.regno = fld_pn; - info->za_tile_vector.index.regno = fld_rm + 12; + info->indexed_za.regno = fld_pn; + info->indexed_za.index.regno = fld_rm + 12; if (fld_tszl & 0x1) imm = (fld_i1 << 3) | (fld_tszh << 2) | (fld_tszl >> 1); @@ -1916,7 +1916,7 @@ aarch64_ext_sme_pred_reg_with_index (const aarch64_operand *self, else return false; - info->za_tile_vector.index.imm = imm; + info->indexed_za.index.imm = imm; return true; } |