aarch64: Add support for xzr register in register pair operands

Analysis of the allowed operand values for `sysp' and `tlbip' reveals
a significant departure from the allowed behavior for operand register
pairs (hitherto labeled AARCH64_OPND_PAIRREG) observed for other
insns in this category.

For instructions `casp', `mrrs' and `msrr' the register pair must
always start at an even index and the second register in the pair is
the index + 1.  This precludes the use of xzr as the first register,
given it corresponds to register number 31.

This is different in the case of `sysp' and `tlbip', however.  These
allow the use of xzr and, where the first operand in the pair is
omitted, this is the default value assigned to it.  When this
operand is assigned xzr, it is expected that the second operand will
likewise take on a value of xzr.

These two instructions therefore "break" two rules of register pairs:

  * The first of the two registers is odd-numbered.
  * The index of the second register is equal to that of the first,
  and not n+1.

To allow for this departure from hitherto standard behavior, we
extend the functionality of the assembler by defining an extension of
the AARCH64_OPND_PAIRREG, called AARCH64_OPND_PAIRREG_OR_XZR.

It is used in defining `sysp' and `tlbip' and allows
`operand_general_constraint_met_p' to allow the pair to both take on
the value of xzr.

1 files changed, 5 insertions, 2 deletions

diff --git a/opcodes/aarch64-dis.c b/opcodes/aarch64-dis.c
index ba1f5dd..8f99259 100644
--- a/opcodes/aarch64-dis.c
+++ b/opcodes/aarch64-dis.c
@@ -302,8 +302,11 @@ aarch64_ext_regno_pair (const aarch64_operand *self ATTRIBUTE_UNUSED, aarch64_op
 		   aarch64_operand_error *errors ATTRIBUTE_UNUSED)
 {
   assert (info->idx == 1
-	  || info->idx ==3);
-  info->reg.regno = inst->operands[info->idx - 1].reg.regno + 1;
+	  || info->idx == 3);
+
+  unsigned prev_regno = inst->operands[info->idx - 1].reg.regno;
+  info->reg.regno = (prev_regno == 0x1f) ? 0x1f
+					 : prev_regno + 1;
   return true;
 }