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AgeCommit message (Expand)AuthorFilesLines
2025-12-09LoongArch: Add support for the ud macro instructionLulu Cai1-0/+1
2025-12-08Fix typo in aarch64-opc.cNick Clifton1-1/+1
2025-12-05Add AMD znver6 processor supportUmesh Kalvakuntla10-3643/+3760
2025-12-05x86: sub-divide APX_F - NCI-NDD-NF and testingJan Beulich2-0/+13
2025-12-05x86: sub-divide APX_F - NFJan Beulich5-391/+419
2025-12-05x86: sub-divide APX_F - NDDJan Beulich5-441/+758
2025-12-05x86: sub-divide APX_F - NCIJan Beulich5-446/+472
2025-12-05x86: correct {RD,WR}{FS,GS}BASE {dis,}assemblyJan Beulich4-9/+39
2025-12-04aarch64: Enable `-M notes' by defaultAlice Carlotti1-2/+2
2025-12-04aarch64: Refactor sysreg operand printingAlice Carlotti1-48/+54
2025-12-04aarch64: Fix incorrect sysreg notes operand notesAlice Carlotti1-2/+4
2025-11-28x86: drop a few excess AVX512VL from opcode tableJan Beulich2-13/+13
2025-11-13PowerPC: Add support for RFC02660 - Context Switch InstructionAbhay Kandpal1-0/+1
2025-11-13PowerPC: Support for Controlled Cluster Memory (RFC02689)Abhay Kandpal1-0/+3
2025-11-07x86: support SALCJan Beulich4-2079/+2090
2025-11-03tidy m4 plugin config supportAlan Modra1-65/+64
2025-10-30s390: Do not generate incomplete opcode tableJens Remus2-2/+4
2025-10-29x86: Disable AMX-TRANSPOSE by defaultHaochen Jiang2-2/+2
2025-10-29Revert "x86/APX: drop AMX-TRANSPOSE promoted insns"Haochen Jiang4-20/+34
2025-10-28PowerPC: Support for Load/Store VSX Vector Paired Byte*32 Indexed (RFC02678)Abhay Kandpal1-0/+4
2025-10-28aarch64: gas: Allow movprfx with fmmla and bfscale [PR gas/33562]Alfie Richards1-13/+13
2025-10-10x86: PadLock adjustmentsJan Beulich5-97/+101
2025-10-10aarch64: Add support for FEAT_SSVE_BITPERMAlice Carlotti1-1/+1
2025-10-10aarch64: Add support for FEAT_SSVE_FEXPAAlice Carlotti1-1/+7
2025-10-10aarch64: Add support for FEAT_SME_MOP4Alice Carlotti7-187/+1923
2025-10-10aarch64: Add support for FEAT_SME_TMOPAlice Carlotti7-430/+654
2025-10-10aarch64: Remove incorrect disassembly constraintAlice Carlotti2-12/+0
2025-10-10aarch64: Use constant fields in simple_index operandsAlice Carlotti6-80/+86
2025-10-10aarch64: Allow multiple fields for sve_aligned_reglistAlice Carlotti6-20/+20
2025-10-10aarch64: Allow multiple fields in {ins|ext}_regnoAlice Carlotti4-8/+7
2025-10-10aarch64: Extend aarch64_field to support constantsAlice Carlotti4-235/+272
2025-10-06aarch64: GICv5 hypervisor control system registersMatthieu Longo1-0/+31
2025-10-06aarch64: GICv5 PPI system registersMatthieu Longo1-0/+32
2025-10-06aarch64: GICv5 CPU interface system registersMatthieu Longo1-0/+13
2025-10-06gas: aarch64: Add instructions for GICv5Saurabh Jha7-2/+89
2025-10-06gas: aarch64: Add flag for GICv5Saurabh Jha1-0/+3
2025-10-06msp430: extended_dst disassemblyAlan Modra1-11/+22
2025-10-04opcodes: PR 33384 invalid disassembler option messageAlan Modra6-171/+164
2025-09-25Binutils: Add clang LTO support to AR and RANLIBH.J. Lu3-15/+395
2025-09-23aarch64: Update system register gatingAlice Carlotti1-485/+485
2025-09-23aarch64: Remove CSRE system registersAlice Carlotti1-12/+0
2025-09-23aarch64: Remove teecr32_el1 and teehbr32_el1Alice Carlotti1-2/+0
2025-09-23aarch64: Add missing system registersAlice Carlotti1-0/+9
2025-09-23aarch64: Add FEAT_SRMASK system registersAlice Carlotti1-0/+24
2025-09-23aarch64: Make spmzr_el0 write-onlyAlice Carlotti1-1/+1
2025-09-23aarch64: Sort aarch64-sys-regs.defAlice Carlotti1-14/+14
2025-09-23aarch64: Remove F_ARCHEXT flagAlice Carlotti3-1290/+1282
2025-09-18Updated and new translations for the binutilsNick Clifton1-220/+228
2025-09-03csky disassembler leakAlan Modra1-0/+1
2025-09-02PowerPC: Vector Instructions for Deeply Compressed Weight for AI (RFC02691)Abhay Kandpal1-0/+22
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