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15 hoursx86/APX: apply NDD-to-legacy transformation to further CMOVcc formsJan Beulich2-31/+34
15 hoursx86/APX: extend TEST-by-imm7 optimization to CTESTccJan Beulich2-31/+31
15 hoursx86/APX: optimize {nf}-form IMUL-by-power-of-2 to SHLJan Beulich2-12/+12
15 hoursx86/APX: optimize certain {nf}-form insns to LEAJan Beulich2-7/+7
15 hoursx86/APX: optimize {nf}-form rotate-by-width-less-1Jan Beulich2-15/+15
15 hoursx86/APX: optimize {nf} forms of ADD/SUB with specific immediatesJan Beulich2-20/+20
19 hoursRISC-V: Add Zabha extension CAS instructions.Jiawei1-0/+8
3 daysaarch64: FP8 scale and convert - Implement minor improvementsVictor Do Nascimento1-12/+12
3 daysaarch64: Treat operand Rt_IN_SYS_ALIASES as register number (PR 31919)Jens Remus1-1/+1
3 daysaarch64: Fix FEAT_B16B16 sve2 instruction constraints.Srinath Parvathaneni2-33/+33
3 daysarch64: Fix the wrong constraint used for sve2p1 instructions.Srinath Parvathaneni1-13/+12
3 daysaarch64: Fix sve2p1 ld[1-4]/st[1-4]q instruction operands.Srinath Parvathaneni5-209/+206
3 daysaarch64: Fix sve2p1 extq instruction operands.Srinath Parvathaneni5-28/+24
3 daysaarch64: Fix sve2p1 dupq instruction operands.Srinath Parvathaneni8-61/+13
4 daysaarch64: Add SME FP8 multiplication instructionsAndrew Carlotti6-834/+1345
4 daysaarch64: Add FP8 Neon and SVE multiplication instructionsAndrew Carlotti8-366/+877
4 daysgas, aarch64: Add SME2 lutv2 extensionsaurabh.jha@arm.com8-100/+208
7 daysx86: optimize {,V}PEXTR{D,Q} with immediate of 0Jan Beulich2-16/+16
7 daysx86: optimize left-shift-by-1Jan Beulich2-52/+52
8 daysx86/APX: fix disassembly of byte register operandsJan Beulich1-0/+1
8 daysRevert "Remove LIBINTL_DEP"Alan Modra3-2/+9
9 daysRemove LIBINTL_DEPAlan Modra3-9/+2
10 daysx86: Remove the secondary encoding for ctest.Cui, Lili2-570/+289
11 daysRISC-V: Add SiFive cease extension v1.0Hau Hsu1-0/+3
11 daysRISC-V: Support Zacas extension.Gianluca Guida1-0/+26
11 daysx86: Fix typo in i386-dis-evex-mod.hCui, Lili1-2/+2
11 daysRemove %ME and used %NE for movbe.Cui, Lili3-10/+14
11 daysSupport APX CCMP and CTESTCui, Lili7-2233/+4165
2024-06-14aarch64: add SPMU system registers missed in f01ae0392edMatthieu Longo1-0/+79
2024-06-12aarch64: add Branch Record Buffer extension instructionsClaudio Bantaloukas6-2448/+2496
2024-06-11MIPS/opcodes: Add MIPS Allegrex DBREAK instructionDavid Guillen Fandos1-1/+1
2024-06-11MIPS/opcodes: Exclude trap instructions for MIPS AllegrexDavid Guillen Fandos1-30/+30
2024-06-10Revert "MIPS/Allegrex: Exclude trap instructions"Maciej W. Rozycki1-30/+30
2024-06-10Revert "MIPS/Allegrex: Enable dbreak instruction"Maciej W. Rozycki1-1/+1
2024-06-10MIPS/Allegrex: Enable dbreak instructionDavid Guillen Fandos1-1/+1
2024-06-10MIPS/Allegrex: Exclude trap instructionsDavid Guillen Fandos1-30/+30
2024-06-10x86/APX: convert ZU to operand constraintJan Beulich4-4223/+4223
2024-06-10x86: disassembler macro for condition codeJan Beulich3-281/+71
2024-06-10x86/APX: support extended SETcc formJan Beulich2-312/+555
2024-06-10x86/APX: add missing CPU requirement to imm+rm forms of <alu2> insnsJan Beulich2-15/+15
2024-06-10autoupdate: regen after replacing obsolete macrosMatthieu Longo1-4/+2
2024-06-10autoupdate: add square brackets around arguments of AC_INITMatthieu Longo1-1/+1
2024-06-10autoupdate: replace obsolete macros AC_AIX, AC_MINIX, and AC_GNU_SOURCEMatthieu Longo1-1/+0
2024-06-06opcodes/riscv: prevent future use of disassemble_info::fprintf_funcAndrew Burgess1-0/+5
2024-06-06opcodes/riscv: add styling support to print_reg_listAndrew Burgess1-14/+37
2024-06-06RISC-V: Add support for Zvfbfwma extensionXiao Zeng1-0/+4
2024-06-06RISC-V: Add support for Zvfbfmin extensionXiao Zeng1-0/+4
2024-06-06RISC-V: Add support for Zfbfmin extensionXiao Zeng1-0/+5
2024-06-05arm: remove disassembly support for the FPA co-processorRichard Earnshaw1-196/+1
2024-06-05Fix illegal memory access when bfd_get_section_contents is called with a NULL...Nick Clifton1-0/+7