aboutsummaryrefslogtreecommitdiff
path: root/opcodes
AgeCommit message (Expand)AuthorFilesLines
20 hoursMIPS objdump: Recognize o64 ABI namesMaximilian Ciric1-0/+9
8 daysriscv disassembler leakAlan Modra1-1/+4
9 daysMIPS objdump: Add `eabi32` and `eabi64` ABI optionsAnghelo Carvajal1-0/+18
10 daysRISC-V: Make SSAMOSWAP.W available for rv64Hau Hsu1-4/+4
12 daysRISC-V: Move all global static target stuff into private data for disassembler.Nelson Chu3-161/+178
2025-02-07x86: Support x86 Zhaoxin PadLock XMODX instructionsMayShao-oc7-4526/+4578
2025-02-05aarch64: Add leading zeros to opcodes in aarch64-tbl.hYury Khrustalev1-143/+143
2025-02-05aarch64: Clean up whitespace in aarch64-tbl.hYury Khrustalev1-280/+280
2025-01-31aarch64: Fix fp8 feature dependenciesAndrew Carlotti1-1/+1
2025-01-31x86/APX: GETSEC cannot be used with REX2Jan Beulich1-1/+1
2025-01-31x86: support RMPREAD insnJan Beulich7-2158/+2211
2025-01-31x86: RMPUPDATE wants operands in different formJan Beulich3-51/+68
2025-01-31x86-64: omit "default" segment prefixes from string insn disassemblyJan Beulich1-5/+8
2025-01-27MicroBlaze: Widen mask used in opcodes/microblaze-dis,cMichael J. Eager1-8/+8
2025-01-27s390: Do not omit vector index register 0 in disassemblyJens Remus1-8/+5
2025-01-23PowerPC: Add support for RFC02657 - AES acceleration instructionsSurya Kumari Jangala1-1/+79
2025-01-20Update translations for various sub-directoriesNick Clifton3-496/+497
2025-01-19Change version to 2.44.50 and regenerate filesNick Clifton2-170/+159
2025-01-19Add markers for bihnutils 2.44 branchNick Clifton1-0/+4
2025-01-17aarch64: Fix sve2p1 gating and add missing instructionsAndrew Carlotti2-333/+457
2025-01-17x86: Add CpuGMISM2 and CpuGMICCSMayShao-oc5-2310/+2326
2025-01-17x86/APX: convert runtime special case to build-time oneJan Beulich2-4/+18
2025-01-17RISC-V: Use t2 for tail if Zicfilp enabledKito Cheng1-0/+1
2025-01-17RISC-V: Support CFI Zicfiss and Zicfilp instructions and CSR.Monk Chiang1-0/+45
2025-01-17RISC-V: Support ssctr/smctr extensions with version 1.0.Nelson Chu1-2/+3
2025-01-17x86: Ignore rounding for vcvt[,u]si2sd under r32 and vcvt[,u]dq2pd instead of...Haochen Jiang2-4/+3
2025-01-16x86: Support x86 Zhaoxin PadLock PHE2 instructionsMayShao-oc7-4496/+4546
2025-01-16disassemble_free_powerpcAlan Modra3-0/+12
2025-01-14x86: Remove "NE" in mnemonics for convert insns related to AI data typesHaochen Jiang4-2133/+2133
2025-01-14x86: Rename VCOMSBF16 to VCOMISBF16Haochen Jiang4-2102/+2102
2025-01-14x86: Remove "P" and "NE" in mnemonics for BF16 arithmetic insnsHaochen Jiang4-2238/+2238
2025-01-14Support Intel AMX-AVX512Haochen Jiang12-1787/+2078
2025-01-14Support Intel AMX-MOVRSHu, Lin111-2622/+2830
2025-01-14Support Intel MOVRSHu, Lin110-2649/+2792
2025-01-14x86: Remove mod_table pass for MVexSIBMEMHaochen Jiang1-28/+18
2025-01-10aarch64: Add support for FEAT_SME_B16B16 feature.Srinath Parvathaneni2-311/+535
2025-01-10aarch64: Add support for FEAT_SVE_B16B16 min and max instructions.Srinath Parvathaneni2-218/+283
2025-01-10aarch64: Add support for FEAT_SVE_B16B16 feature.Srinath Parvathaneni1-14/+14
2025-01-10aarch64: Make VGx4 symbol mandatory for fvdotb and fvdottAndrew Carlotti1-2/+2
2025-01-10aarch64: Rename AARCH64_OPND_SME_ZT0_INDEX2_12Andrew Carlotti3-5/+5
2025-01-10aarch64: Remove redundant sme-lutv2 qualifiers and operandsAndrew Carlotti6-96/+70
2025-01-10aarch64: Fix incorrect gating of sme-lutv2 instructionsAndrew Carlotti1-4/+10
2025-01-10aarch64: Add support for FEAT_SME_F16F16 fcvt and fcvtl instructions.Srinath Parvathaneni2-218/+246
2025-01-10aarch64: Add support for FEAT_SME_F16F16 fmla and fmls instructions.Srinath Parvathaneni2-286/+430
2025-01-10aarch64: Add support for FEAT_SME_F16F16 fmops and fmopa instructions.Srinath Parvathaneni2-185/+221
2025-01-10x86: Support x86 Zhaoxin PadLockRNG2 instructionMayShao-oc7-4432/+4483
2025-01-09RISC-V: Fix display of partial instructionsCharlie Jenkins1-4/+49
2025-01-08Support Intel AMX-FP8Liwei Xu7-1058/+1179
2025-01-06x86/APX: simplify ENQCMD[,S} opcode table entriesJan Beulich2-8/+8
2025-01-02Support Intel AMX-TF32Haochen Jiang7-1090/+1172
generated by cgit v1.1 at 2025-02-23 16:41:43 +0000