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| author | Andrew Carlotti <andrew.carlotti@arm.com> | 2024-06-21 19:31:34 +0100 |
|---|---|---|
| committer | Richard Earnshaw <rearnsha@arm.com> | 2024-06-24 16:50:28 +0100 |
| commit | 59b78ab1c16356c2b5a9a1cba40c4029f84ed409 (patch) | |
| tree | 1d3f3d5321777f0aa1337bd64c19cf026b11bd1c /opcodes/aarch64-dis.c | |
| parent | 05f15256d0274b8321eec4cad4273340e1a8521f (diff) | |
| download | binutils-59b78ab1c16356c2b5a9a1cba40c4029f84ed409.zip binutils-59b78ab1c16356c2b5a9a1cba40c4029f84ed409.tar.gz binutils-59b78ab1c16356c2b5a9a1cba40c4029f84ed409.tar.bz2 | |
aarch64: Add FP8 Neon and SVE multiplication instructions
This includes all the instructions under the following features:
- FEAT_FP8FMA (+fp8fma)
- FEAT_FP8DOT4 (+fp8dot4)
- FEAT_FP8DOT2 (+fp8dot2)
- FEAT_SSVE_FP8FMA (+ssve-fp8fma)
- FEAT_SSVE_FP8DOT4 (+ssve-fp8dot4)
- FEAT_SSVE_FP8DOT2 (+ssve-fp8dot2)
Diffstat (limited to 'opcodes/aarch64-dis.c')
| -rw-r--r-- | opcodes/aarch64-dis.c | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/opcodes/aarch64-dis.c b/opcodes/aarch64-dis.c index 045af49..6098204 100644 --- a/opcodes/aarch64-dis.c +++ b/opcodes/aarch64-dis.c @@ -402,6 +402,12 @@ aarch64_ext_reglane (const aarch64_operand *self, aarch64_opnd_info *info, info->reglane.index = extract_fields (code, 0, 2, FLD_H, FLD_L); info->reglane.regno &= 0x1f; break; + case AARCH64_OPND_QLF_S_2B: + /* h:l:m */ + info->reglane.index = extract_fields (code, 0, 3, FLD_H, FLD_L, + FLD_M); + info->reglane.regno &= 0xf; + break; default: return false; } @@ -422,7 +428,15 @@ aarch64_ext_reglane (const aarch64_operand *self, aarch64_opnd_info *info, return 0; switch (info->qualifier) { + case AARCH64_OPND_QLF_S_B: + /* H:imm3 */ + info->reglane.index = extract_fields (code, 0, 2, FLD_H, + FLD_imm3_19); + info->reglane.regno &= 0x7; + break; + case AARCH64_OPND_QLF_S_H: + case AARCH64_OPND_QLF_S_2B: if (info->type == AARCH64_OPND_Em16) { /* h:l:m */ @@ -437,6 +451,7 @@ aarch64_ext_reglane (const aarch64_operand *self, aarch64_opnd_info *info, } break; case AARCH64_OPND_QLF_S_S: + case AARCH64_OPND_QLF_S_4B: /* h:l */ info->reglane.index = extract_fields (code, 0, 2, FLD_H, FLD_L); break; |