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2023-10-18Changing it so Zalasr has one bit hardcoded for each, to reduce opcode confus...brs1-8/+8
2023-10-18Adding load-acquire/store-release. Note they are written here as `lb.` for th...brs1-0/+8
2023-10-17Add pseudo-instructions for Zimop/Zcmop (#194)Ved Shanbhogue3-51/+114
2023-10-17Merge pull request #202 from a4lg/remove-zvamoAndrew Waterman1-41/+0
2023-10-16Remove unratified 'Zvamo' instructions from rv_vTsukasa OI1-41/+0
2023-10-09Merge pull request #200 from felixhauptmann/masterAndrew Waterman2-131/+131
2023-10-10fix csv parsingFelix Hauptmann2-131/+131
2023-09-28Merge pull request #198 from sequencer/sdextNeel Gala1-0/+0
2023-09-28rename rv_debug to rv_sdextJiuyang Liu1-0/+0
2023-09-27Merge pull request #197 from sequencer/split_debugAndrew Waterman2-1/+2
2023-09-27split dret from rv_system to rv_debugJiuyang Liu2-1/+2
2023-09-26Merge pull request #195 from sequencer/constant_csvAndrew Waterman5-611/+590
2023-09-25split arg_lut, causes, csr, csr32 from constants.pyJiuyang Liu5-611/+590
2023-09-24Merge pull request #196 from sequencer/patch-1Andrew Waterman1-1/+0
2023-09-25Remove duplicate zimmJiuyang Liu1-1/+0
2023-09-23Merge pull request #193 from riscv/fix-changes-in-189Neel Gala1-0/+3
2023-09-20retain the original shift instructions as pseudo-ops as wellNeel Gala1-0/+3
2023-09-19Merge pull request #192 from sequencer/fix_dupAndrew Waterman1-5/+5
2023-09-20fix instruction duplication between rv128_c and rv64_cJiuyang Liu1-5/+5
2023-09-16Merge pull request #189 from charlie-rivos/support_rv32_shiftAndrew Waterman1-3/+3
2023-09-16Merge pull request #188 from charlie-rivos/fix_c_addiwAndrew Waterman2-7/+4
2023-09-15Generate compressed shift instructions for rv32Charlie Jenkins1-3/+3
2023-09-15C.ADDIW cannot have an rd of 0Charlie Jenkins2-7/+4
2023-09-15Merge pull request #187 from ved-rivos/zimopAndrew Waterman2-0/+62
2023-09-15add unratified Zcmop instructionsVed Shanbhogue1-0/+13
2023-09-15add unratified Zimop instructionsVed Shanbhogue1-0/+49
2023-08-13Merge pull request #186 from ved-rivos/svadu1Andrew Waterman1-4/+4
2023-08-13Svadu: Rename HADE to ADUEVed Shanbhogue1-4/+4
2023-07-31rv64_q_zfa: rs2 is variable field.Nikola Rajovic1-1/+1
2023-07-31rv32_d_zfa: rs2 is variable field.Nikola Rajovic1-1/+1
2023-07-25Merge pull request #181 from rivosinc/add_smcntrpmf_csrsAndrew Waterman1-0/+4
2023-07-25Merge pull request #182 from nrajovic/fix_vector_mask_register_logical_instru...Andrew Waterman1-8/+8
2023-07-25rv_v: fix for Vector Mask-Register Logical instructions.Nikola Rajovic1-8/+8
2023-07-24Add Smcntrpmf CSRsAtul Khare1-0/+4
2023-07-12Merge branch 'rivosinc-smdeleg_definitions'Andrew Waterman2-0/+14
2023-07-12Add Smcdeleg CSR+constantsAtul Khare2-0/+14
2023-07-10Merge pull request #178 from rivosinc/smcsrind_sscsrind_csrsAndrew Waterman1-0/+15
2023-07-10Add Smcsrind/Sscsrind CSRsAtul Khare1-0/+15
2023-05-26Merge pull request #177 from liweiwei90/plct-bf16-devNeel Gala1-2/+2
2023-05-19Update encodings for vfwmaccbf16.vv/vfWeiwei Li1-2/+2
2023-05-15Merge pull request #176 from ved-rivos/zacasNeel Gala2-0/+3
2023-05-13add amocas.q (RV64 only) zacas instructionVed Shanbhogue1-0/+1
2023-05-13add amocas.w/d zacas instructionsVed Shanbhogue1-0/+2
2023-05-02Merge pull request #167 from Lucas-Wye/masterNeel Gala1-2/+28
2023-05-02Merge pull request #154 from rivosinc/zvk-vector-cryptoNeel Gala14-8/+218
2023-05-01Support for Zvk, Vector Cryptography ExtensionsEric Gouriou14-8/+218
2023-04-19Merge pull request #174 from liweiwei90/plct-bf16-devAndrew Waterman3-0/+6
2023-04-15Add (unratified) BF16(Zfbfmin/Zvfbfmin/Zvfbfwma) extensions.Weiwei Li3-0/+6
2023-04-07Merge pull request #172 from dramforever/instr_dict_extension_fixNeel Gala1-6/+8
2023-04-07Fix merging of instructions with the same namedramforever1-6/+8
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