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| author | Chih-Min Chao <48193236+chihminchao@users.noreply.github.com> | 2026-04-30 14:37:31 +0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2026-04-29 23:37:31 -0700 |
| commit | 0a0851807361b9ae61d877cea02ce877a7af8395 (patch) | |
| tree | cad6d037334043c93836b75f58c79f92c4660fc6 | |
| parent | ee0f7fead9bfd548b66dc0ae61734d717941b78c (diff) | |
| download | riscv-opcodes-master.tar.gz riscv-opcodes-master.tar.bz2 riscv-opcodes-master.zip | |
The opcode[1:0] should 3 but not 2 for 32bits encoding
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
| -rw-r--r-- | extensions/unratified/rv32_p | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/extensions/unratified/rv32_p b/extensions/unratified/rv32_p index 0e6f5ef..aa4be20 100644 --- a/extensions/unratified/rv32_p +++ b/extensions/unratified/rv32_p @@ -112,7 +112,7 @@ wsll 31=0 30..28=0x0 27=1 26..25=0x3 rs2 rs1 14..12=0x2 p_rd_p 7. pwsla.bs 31=0 30..28=0x4 27=1 26..25=0x0 rs2 rs1 14..12=0x2 p_rd_p 7..0=0x1b pwsla.hs 31=0 30..28=0x4 27=1 26..25=0x1 rs2 rs1 14..12=0x2 p_rd_p 7..0=0x1b -wsla 31=0 30..28=0x4 27=1 26..25=0x3 rs2 rs1 14..12=0x2 p_rd_p 7..0=0x1a +wsla 31=0 30..28=0x4 27=1 26..25=0x3 rs2 rs1 14..12=0x2 p_rd_p 7..0=0x1b wzip8p 31=0 30..28=0x7 27=1 26..25=0x0 rs2 rs1 14..12=0x2 p_rd_p 7..0=0x1b wzip16p 31=0 30..28=0x7 27=1 26..25=0x1 rs2 rs1 14..12=0x2 p_rd_p 7..0=0x1b |