* Revise instructions for regeneration, not to create executables.
* Add instructions to regenerate both object files and test vectors
(except for `mcdc-general-none.proftext`)
* Reformat

The RTBS_None option in Clang-format avoids breaking after a short
return type.
However, there was an issue with the behaviour in that it wouldn't take
the leading indentation of the line into account.
This meant that the behaviour wasn't applying when intended.

In order to address this situation without breaking the existing
formatting, RTBS_None has been deprecated.
In its place are two new options for AlwaysBreakAfterReturnType.
The option RTBS_Automatic will break after the return type based on
PenaltyReturnTypeOnItsOwnLine.
The option RTBS_ExceptShortType will take the leading indentation into
account and prevent breaking after short return types.

This allows the inconsistent behaviour of RTBS_None to be avoided and
users to decide whether they want to allow breaking after short return
types or not.

Resolves #78010

The implementation of `FormatCache::Entry
&FormatCache::GetEntry(ConstString)` is effectively a duplication of
`std::map::operator[]`. This change deletes `GetEntry` and replaces its
use with `operator[]`.

To register the conversion the autogenerated function
`registerSCFToEmitC()` calls `createSCFToEmitC()`, which itself is also
autogenerated. The removed function, however, isn't used in the upstream
codebase.

This patch will also expand supports for attribute/target, while
the priority of newly supported ISAs will be set to zero.

This patch replaces min/max intrinsic with one of its operands if
possible.
Alive2: https://alive2.llvm.org/ce/z/LoHfYf
Fixes #75155.

Previously we stored MachineInstr which restricted the implementation
to only handle operand 0.

The TH_LWD instruction has two sign extended destinations.

table.grow is valid with type `[t i32] -> [i32]`.
Fixes: #79966.

Modifying a cherry-picked patch to fix code formatting issues can be
risky, so we don't typically do this. Therefore, it's not necessary to
run this job on the release branches.

This action is really just a wrapper around cmake and ninja. It doesn't
add any value to the builds, and I don't think we need it now that there
are reusable workflows.

Implement handling of get/set floating point environment for ARM in
Global Instruction Selector. Lowering of these intrinsics to operations
on FPSCR was previously inplemented in DAG selector, in GlobalISel it is
reused.

This adds GCC-compatible names for code model selection on 64-bit SPARC
with absolute code.
Testing with a 2-stage build then running codegen tests works okay under
all of the supported code models.

(32-bit target does not have selectable code models)

Reviewed By: @brad0, @MaskRay 

According to the C++ standard, `dynamic_cast` of pointers either returns
a pointer (7.6.1.7) or results in undefined behavior (11.9.5). This
patch marks `__dynamic_cast` as `willreturn` to remove unused calls.

Fixes #77606.

We had the isel patterns, but no tests that used them. We only had
sextload and zextload tests.

Also reduce the alignment on some of the test cases that were
unnecessarily over aligned.

For the current version of the PR43024 test, we should be able to
optimize away the operations but fail to do so. This commit adds a
strictfp version of the test where we should not be able to optimize
away the operations, as a verification that changes to improve the other
effect have no adverse effect.

This reapplies #76657. Non-trivial elements didn't get destroyed
previously. This fixes the bug and adds tests for all the vector
insertion functions.

This patch folds:
```
(icmp eq (and (bitcast X to int), ExponentMask), ExponentMask) --> llvm.is.fpclass(X, fcInf|fcNan)
(icmp ne (and (bitcast X to int), ExponentMask), ExponentMask) --> llvm.is.fpclass(X, ~(fcInf|fcNan))
```
Alive2: https://alive2.llvm.org/ce/z/_hXAAF

This is needed with RV64LegalI32 when the setcc is created after type
legalization. An i1 xor would have been promoted to i32, but the setcc
would have i64 result.

Summary:
The current logic tries to map target mapping tables to the current
device. Right now it assumes that data is only mapped a single time per
device. This is only true if we have a single instance of the runtime
running on a single program. However, in the case of dynamic library
loads or shared libraries, this may happen multiple times.

Given a case of a simple dynamic library load which has its own target
kernel instruction, the current logic had only the first call to
`__tgt_target_kernel` to the data mapping for that device. Then, when
the next dynamic library load got called, it would see that the global
were already mapped for that device and skip registering its own
entires, even though they were distinct. This resulted in none of the
mappings being done and hitting an assertion.

This patch simply gets rid of this per-device check. The check should
instead be on the host offloading entries. We already have logic that
calls `continue...

This matches the non-rv64-legal-i32 version.

The default legalization uses 2 compares and an xor. We can instead
use add+addw+xor+snez like we do without RV64LegaI32.

The default lowering will use shifts to make use of an i32 setcc.
We don't support i32 setcc, so its better to sig extend the low
32 bits and compare the full 64 bit result. This gives produces
mul+mulw+xor+snez like we do without RV64LegalI32.

A collection of tests from #69152 and for constant offsets with scalable typesizes.