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2020-09-11Fix possible exception list for FCVT.D.S and FCVT.S.DAndrew Waterman1-2/+2
2020-09-01Add changelog entry for a1eab4cbb0f30cdafd77e3d540b3c38851d78b02Andrew Waterman1-0/+2
2020-09-01PMP changes don't need an sfence only when page-based virtual memory is not i...gfavor1-1/+1
2020-08-28Add scontext, hcontext, and mcontext CSRs for Debug (#559)Ernie Edgar1-0/+9
2020-08-25Change "read-only alias" to "read-only copy" (#572)John Hauser1-1/+1
2020-08-25Change "hardwired to other field" to "read-only field" (#571)John Hauser3-18/+19
2020-08-25Rename empty regions to vacant regions for consistency with unpriv specAndrew Waterman1-4/+4
2020-08-24TweakAndrew Waterman1-2/+2
2020-08-24Clarify that ASIDs are (currently) local to a hartAndrew Waterman2-15/+13
2020-08-23Clarify description of CB formatAndrew Waterman1-2/+2
2020-08-18Remove assembly manualAndrew Waterman4-168/+10
2020-08-14Change "reserved for custom" to "designated for custom" (#566)John Hauser9-30/+30
2020-08-14Improve table of conditions for explicit CSR read/write (#564)John Hauser1-15/+18
2020-08-14Improve table of RAS hints for JALR instructions (#563)John Hauser1-10/+11
2020-08-14Improve table of trap characteristics in introduction (#562)John Hauser1-6/+8
2020-08-13Merge pull request #547 from jhauser-us/jhauser-CSRSideEffects3Andrew Waterman1-0/+25
2020-08-13Merge pull request #531 from jhauser-us/jhauser-CSRRulesAndrew Waterman1-15/+28
2020-08-12mcounteren only exists if U-mode existsAndrew Waterman1-0/+2
2020-08-03Fix formatting of 2^XLENAndrew Waterman3-9/+9
2020-07-31Add missing wordAndrew Waterman1-1/+1
2020-07-31Clarify that ASID changes are also immediateAndrew Waterman1-0/+1
2020-07-31Clarify that satp.MODE transitions to/from Bare don't require SFENCE.VMAAndrew Waterman1-0/+3
2020-07-31Reserve some satp encodings for custom useAndrew Waterman1-5/+11
2020-07-30Fix Sv48 VALEN typo (#551)Daniel Lustig1-1/+1
2020-07-30Further clarified the program order of CSR accessesJohn Hauser1-4/+10
2020-07-27Clarify effect on unwritten bits for CSRRS/CSRRCAndrew Waterman1-4/+3
2020-07-26Clarify which implicit reads of the translation structures are allowedAndrew Waterman1-1/+2
2020-07-25tweakAndrew Waterman1-1/+1
2020-07-25Add commentary about caching invalid PTEsAndrew Waterman1-0/+7
2020-07-23Add examples for CSR side effects and indirect effectsJohn Hauser1-0/+25
2020-07-22Clarify what is a side effect of a CSR access (#546)John Hauser1-7/+14
2020-07-22Pmp wording fix (#545)Stef O'Rear6-25/+26
2020-07-20clarify that high counters are RV32I-onlyAndrew Waterman1-1/+1
2020-07-20Make it explicit that the priv arch requires ZicsrAndrew Waterman1-3/+9
2020-07-19Add missing wordAndrew Waterman1-1/+1
2020-07-17Remove redundant phrase from access-/page-fault textAndrew Waterman2-2/+2
2020-06-28Clarifications to the perceived ordering of CSR accesses and their effectsJohn Hauser1-13/+20
2020-06-10Fix prefaceAndrew Waterman1-2/+2
2020-06-10Priority of misaligned load/store address checks is implementation-definedAndrew Waterman2-1/+21
2020-06-04FADD/FSUB can't raise UF, hence, no PPO dependenceAndrew Waterman1-4/+4
2020-06-04Fix unclarity in MPRV definition introduced by 569d07195a8495460f04592d845515...Andrew Waterman1-1/+1
2020-05-22Extend PMP scheme to support 64 regionsAndrew Waterman3-28/+51
2020-05-21Merge pull request #523 from jhauser-us/jhauser-hstatusVTWAndrew Waterman1-21/+14
2020-05-18Clarify that satp.MODE=Bare with satp.LSBs != 0 is unspecified for nowAndrew Waterman1-0/+3
2020-05-14Add VTW field to hstatus; improve rules for WFI in virtual modesJohn Hauser1-21/+14
2020-05-14Merge pull request #518 from jhauser-us/jhauser-virtualinstexceptionAndrew Waterman1-13/+90
2020-05-13Expand the circumstances that raise virtual instruction exceptionsJohn Hauser1-18/+20
2020-05-11Improve description of RV64 *W instructionsAndrew Waterman1-7/+8
2020-05-05Clarify that _coherent_ main memory regions use RVWMO or RVTSOAndrew Waterman1-2/+4
2020-05-05Add virtual instruction exceptions to the hypervisor extensionJohn Hauser1-12/+87
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