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| author | Andrew Waterman <andrew@sifive.com> | 2020-07-26 16:15:04 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2020-07-26 16:15:04 -0700 |
| commit | e4f6e44f5c560561b88b92cf4c01080fb6d7525d (patch) | |
| tree | 02a89bab97cbbdc15cce2dce7e4fa0385d582d94 /src | |
| parent | a8e4745481b4b77f29f7316b2d44192c0adfa857 (diff) | |
| download | riscv-isa-manual-e4f6e44f5c560561b88b92cf4c01080fb6d7525d.zip riscv-isa-manual-e4f6e44f5c560561b88b92cf4c01080fb6d7525d.tar.gz riscv-isa-manual-e4f6e44f5c560561b88b92cf4c01080fb6d7525d.tar.bz2 | |
Clarify which implicit reads of the translation structures are allowed
Diffstat (limited to 'src')
| -rw-r--r-- | src/supervisor.tex | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/supervisor.tex b/src/supervisor.tex index 5982bff..fa0fe9b 100644 --- a/src/supervisor.tex +++ b/src/supervisor.tex @@ -1103,7 +1103,8 @@ additional page faults. Implementations must only perform implicit reads of the translation data structures pointed to by the current contents of the {\tt satp} -register, and must only raise exceptions for implicit accesses that are +register or a subsequent valid (V=1) translation data structure entry, +and must only raise exceptions for implicit accesses that are generated as a result of instruction execution, not those that are performed speculatively. |