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| author | Ernie Edgar <43148441+ernie-sifive@users.noreply.github.com> | 2020-08-28 20:15:09 -0600 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-08-28 19:15:09 -0700 |
| commit | c1599335d98b49af6bc8e6612041897282f8a43b (patch) | |
| tree | 9e4743b8a08f8b1a99ddd1fa72b96fe5638d0564 /src | |
| parent | bb5537941b2bc31acbf111d9261ee6da1aae4a50 (diff) | |
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Add scontext, hcontext, and mcontext CSRs for Debug (#559)
* Add scontext, hcontext, and mcontext CSRs
These registers may be written with process ID information by operating systems running in their respective privilege levels. A debugger may use tdata3 (aka textra) to qualify breakpoints based on a comparison of context register(s) with corresponding trigger fields.
* Move scontext and hcontext to appropriate sections of CSR table
* Remove reserved ranges for additional debug CSRs
Diffstat (limited to 'src')
| -rw-r--r-- | src/priv-csrs.tex | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/src/priv-csrs.tex b/src/priv-csrs.tex index 6dcf7f2..c1bd6d8 100644 --- a/src/priv-csrs.tex +++ b/src/priv-csrs.tex @@ -222,6 +222,10 @@ Number & Privilege & Name & Description \\ \hline \tt 0x180 & SRW &\tt satp & Supervisor address translation and protection. \\ \hline +\multicolumn{4}{|c|}{Debug/Trace Registers} \\ +\hline +\tt 0x5A8 & SRW &\tt scontext & Supervisor-mode context register. \\ +\hline \end{tabular} \end{center} \caption{Currently allocated RISC-V supervisor-level CSR addresses.} @@ -256,6 +260,10 @@ Number & Privilege & Name & Description \\ \hline \tt 0x680 & HRW &\tt hgatp & Hypervisor guest address translation and protection. \\ \hline +\multicolumn{4}{|c|}{Debug/Trace Registers} \\ +\hline +\tt 0x6A8 & HRW &\tt hcontext & Hypervisor-mode context register. \\ +\hline \multicolumn{4}{|c|}{Hypervisor Counter/Timer Virtualization Registers} \\ \hline \tt 0x605 & HRW &\tt htimedelta & Delta for VS/VU-mode timer. \\ @@ -375,6 +383,7 @@ Number & Privilege & Name & Description \\ \tt 0x7A1 & MRW &\tt tdata1 & First Debug/Trace trigger data register. \\ \tt 0x7A2 & MRW &\tt tdata2 & Second Debug/Trace trigger data register. \\ \tt 0x7A3 & MRW &\tt tdata3 & Third Debug/Trace trigger data register. \\ +\tt 0x7A8 & MRW &\tt mcontext & Machine-mode context register. \\ \hline \multicolumn{4}{|c|}{Debug Mode Registers } \\ \hline |