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| author | Andrew Waterman <andrew@sifive.com> | 2020-08-12 14:46:44 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2020-08-12 14:46:58 -0700 |
| commit | 1eaebccc78d88f110a68faf1b39938fc291a4065 (patch) | |
| tree | a9878ee09408f4c99c593a096ecffeb256b779f0 /src | |
| parent | d9ea1ca369d6f1f8e61644b0bb87416a4f2857d8 (diff) | |
| download | riscv-isa-manual-1eaebccc78d88f110a68faf1b39938fc291a4065.zip riscv-isa-manual-1eaebccc78d88f110a68faf1b39938fc291a4065.tar.gz riscv-isa-manual-1eaebccc78d88f110a68faf1b39938fc291a4065.tar.bz2 | |
mcounteren only exists if U-mode exists
Resolves #561
Diffstat (limited to 'src')
| -rw-r--r-- | src/machine.tex | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/machine.tex b/src/machine.tex index a718611..d7a53be 100644 --- a/src/machine.tex +++ b/src/machine.tex @@ -1885,6 +1885,8 @@ into loads to the memory-mapped {\tt mtime} register, or emulate this functionality in M-mode software. \end{commentary} +In systems without U-mode, the {\tt mcounteren} register should not exist. + \subsection{Machine Counter-Inhibit CSR ({\tt mcountinhibit})} \begin{figure*}[h!] |