Clarify what is a side effect of a CSR access (#546)

1 files changed, 14 insertions, 7 deletions

diff --git a/src/csr.tex b/src/csr.tex
index f309913..b1b7336 100644
--- a/src/csr.tex
+++ b/src/csr.tex
@@ -76,8 +76,8 @@ writable.  Other bits in the CSR are unaffected.
 
 For both CSRRS and CSRRC, if {\em rs1}={\tt x0}, then the instruction
 will not write to the CSR at all, and so shall not cause any of the
-side effects that might otherwise occur on a CSR write, such as
-raising illegal instruction exceptions on accesses to read-only CSRs.
+side effects that might otherwise occur on a CSR write, nor
+raise illegal instruction exceptions on accesses to read-only CSRs.
 Both CSRRS and CSRRC always read the addressed CSR and cause any read
 side effects regardless of {\em rs1} and {\em rd} fields.  Note that
 if {\em rs1} specifies a register holding a zero value other than {\tt
@@ -92,8 +92,9 @@ value obtained by zero-extending a 5-bit unsigned immediate (uimm[4:0]) field
 encoded in the {\em rs1} field instead of a value from an integer
 register.  For CSRRSI and CSRRCI, if the uimm[4:0] field is zero, then
 these instructions will not write to the CSR, and shall not cause any
-of the side effects that might otherwise occur on a CSR write.  For
-CSRRWI, if {\em rd}={\tt x0}, then the instruction shall not read the
+of the side effects that might otherwise occur on a CSR write, nor raise
+illegal instruction exceptions on accesses to read-only CSRs.
+For CSRRWI, if {\em rd}={\tt x0}, then the instruction shall not read the
 CSR and shall not cause any of the side effects that might occur on a
 CSR read.  Both CSRRSI and CSRRCI will always read the CSR and cause
 any read side effects regardless of {\em rd} and {\em rs1} fields.
@@ -130,10 +131,16 @@ Instruction & rd   & uimm & read CSR? & write CSR? \\
 Table~\ref{tab:csrsideeffects} summarizes the behavior of the CSR
 instructions with respect to whether they read and/or write the CSR.
 
+For any event or consequence that occurs due to a CSR having a particular
+value, if a write to the CSR gives it that value, the resulting event or
+consequence is said to be an \emph{indirect effect} of the write.
+Indirect effects of a CSR write are not considered by the RISC-V ISA to
+be side effects of that write.
+
 \begin{commentary}
-  The CSRs defined so far do not have any architectural side effects on reads
-  beyond raising illegal instruction exceptions on disallowed accesses.
-  Custom extensions might add CSRs with side effects on reads.
+  The CSRs defined so far in this volume
+  do not have any architectural side effects on reads or writes.
+  Custom extensions might add CSRs for which accesses have side effects.
 \end{commentary}
 
 Some CSRs, such as the instructions-retired counter, {\tt instret},