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| author | Andrew Waterman <andrew@sifive.com> | 2020-06-04 16:07:03 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2020-06-04 16:07:36 -0700 |
| commit | 3921122cf3cc1257c61901f2acba1a1f6d316575 (patch) | |
| tree | e7b7bfeba358c6b334c26c3570625212c97ed732 /src | |
| parent | a22c84f1147a230b32fbec7d578b3a71b2062cd4 (diff) | |
| download | riscv-isa-manual-3921122cf3cc1257c61901f2acba1a1f6d316575.zip riscv-isa-manual-3921122cf3cc1257c61901f2acba1a1f6d316575.tar.gz riscv-isa-manual-3921122cf3cc1257c61901f2acba1a1f6d316575.tar.bz2 | |
Fix unclarity in MPRV definition introduced by 569d07195a8495460f04592d8455153f730a0f54
Resolves #528
Diffstat (limited to 'src')
| -rw-r--r-- | src/machine.tex | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/machine.tex b/src/machine.tex index 9e20ee5..0ea6820 100644 --- a/src/machine.tex +++ b/src/machine.tex @@ -670,7 +670,7 @@ widest supported width not wider than the new MXLEN. \subsubsection{Memory Privilege in {\tt mstatus} Register} The MPRV (Modify PRiVilege) bit modifies the privilege level at which loads -and stores execute in all privilege modes. When MPRV=0, loads and stores +and stores execute. When MPRV=0, loads and stores behave as normal, using the translation and protection mechanisms of the current privilege mode. When MPRV=1, load and store memory addresses are translated and protected, and |