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:
riscv-isa-manual.git
1437-update-generated-filenames-to-be-more-desciptive
1454-fix-merge-and-release-workflow
1532-lack-of-list-of-figures-tables
Sv57
Svinval
Svnapot
Svpbmt
antora-refactor
aswaterman-patch-1
atomics-wording-v2
bonzini-hpmdelta
cnop
convert2adoc_rvwmo
csr-wip
fix-adoc-IDs
hypervisor
kersten1-patch-3
latex
lrsc
main
misa-ztso
msip
mtime-optional
n-ext
pmp
ratified-priv-v1.11-sans-hypervisor-draft
sail-inclusion-example
sfence-asid
smpmpmt
svkt
tmp
trap
v20240411
virtual-memory
wfmi
zam
zfb
ztso-ratification
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preface.tex
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2023-04-04
Removed remaining latex.
Bill Traynor
1
-428
/
+0
2023-02-28
V extension is frozen
Bill Traynor
1
-1
/
+1
2023-02-28
Zihintntl is now frozen
Bill Traynor
1
-1
/
+1
2022-11-04
Standardize on {\tt pc}, rather than PC
Andrew Waterman
1
-2
/
+2
2022-07-26
Zmmul is ratified and is now version 1.0
Andrew Waterman
1
-0
/
+1
2022-07-26
Add Zihintntl spec (#810)
Andrew Waterman
1
-0
/
+1
2022-07-26
Zhinxmin is ratified, too
Andrew Waterman
1
-1
/
+1
2022-07-26
Update version numbers for Zfh/Zfinx
Andrew Waterman
1
-5
/
+5
2021-08-02
Ratified Zihintpause is version 2.0
Andrew Waterman
1
-1
/
+1
2021-08-02
Fix format for ratified Zihintpause in preface table, part 2
John Hauser
1
-1
/
+1
2021-08-02
Fix format for ratified Zihintpause in preface table
John Hauser
1
-1
/
+1
2021-08-02
Zihintpause is ratified
John Hauser
1
-1
/
+1
2021-08-02
Update status of various extensions
John Hauser
1
-0
/
+15
2020-10-17
Add PAUSE instruction
Andrew Waterman
1
-0
/
+1
2020-07-22
Pmp wording fix (#545)
Stef O'Rear
1
-1
/
+1
2020-03-16
Add preface section for older version 20191213
Andrew Waterman
1
-0
/
+55
2019-12-13
A extension v2.1 has been ratified
Ratified-IMAFDQC
Andrew Waterman
1
-1
/
+3
2019-07-23
Fix extension ordering in naming chapter and preface
Andrew Waterman
1
-3
/
+3
2019-07-21
Move N extension into its own chapter in the priv spec
Andrew Waterman
1
-1
/
+1
2019-06-24
Fix spelling
Andrew Waterman
1
-2
/
+2
2019-06-21
Changes to unprivileged spec for bi[g]-endian support
Andrew Waterman
1
-0
/
+7
2019-06-21
Bump version of unprivileged spec to 20190621-draft
Andrew Waterman
1
-0
/
+50
2019-06-08
Updated preface to indicate this is now ratified spec.
Krste Asanovic
1
-18
/
+18
2019-03-24
Improve CSR ordering section
Andrew Waterman
1
-2
/
+2
2019-03-05
Version 20190305-Base-Ratification for ratification vote.
Krste Asanovic
1
-4
/
+9
2018-11-27
Add Hauser's definition of "memory access"
Andrew Waterman
1
-1
/
+1
2018-11-06
spelling
20181106-Base-Ratification
Andrew Waterman
1
-1
/
+1
2018-11-06
Version ready for ratification process.
Krste Asanovic
1
-16
/
+11
2018-11-06
Updated status of counters. Not ready for ratification as there are issues o...
Krste Asanovic
1
-1
/
+5
2018-11-06
Allow access exceptions to be reported on misaligned atomic memory operations...
Krste Asanovic
1
-0
/
+2
2018-11-06
Bumped base I version number to 2.1 to reflect ratified memory model, exclusi...
Krste Asanovic
1
-2
/
+6
2018-11-06
Moved zifencetso back into main I chapter, as does not extend base ISA spec.
Krste Asanovic
1
-2
/
+0
2018-11-06
Gave CSR instruction module a name and a version, and made clear these are be...
Krste Asanovic
1
-3
/
+4
2018-11-05
Merge branch 'master' of github.com:riscv/riscv-isa-manual
Krste Asanovic
1
-13
/
+13
2018-11-05
Update preface for unemulatable misaligned excpetions reported as access exce...
Krste Asanovic
1
-1
/
+2
2018-11-05
tweaks
Andrew Waterman
1
-11
/
+11
2018-11-05
Fix spelling
Andrew Waterman
1
-2
/
+2
2018-11-04
Moved FENCE.I out of base I chapter into separate Zifencei chapter.
Krste Asanovic
1
-32
/
+47
2018-11-04
Made clear fence.tso is an optional extension
Krste Asanovic
1
-2
/
+2
2018-11-03
Removed text regarding big or bi-endian operation. For now, only specifying ...
Krste Asanovic
1
-0
/
+2
2018-08-28
F/D extensions to v2.2
Andrew Waterman
1
-2
/
+6
2018-08-26
Updated several "user" references to "unprivileged".
Krste Asanovic
1
-6
/
+7
2018-08-07
Made cleanup pass over floating-point extensions
Krste Asanovic
1
-1
/
+4
2018-08-07
Broke out actual perf counters into separate chapter.
Krste Asanovic
1
-1
/
+1
2018-08-06
Cleaned up RV64 chapter to remove platform-specific mandates.
Krste Asanovic
1
-0
/
+7
2018-08-05
Provide new description of misaligned load/store behavior compatible with pri...
Krste Asanovic
1
-1
/
+8
2018-08-05
update preface.
Krste Asanovic
1
-1
/
+2
2018-07-06
Changes to intro as part of rationalizing ISA into ISA-only versus platform-m...
Krste Asanovic
1
-2
/
+7
2018-05-30
Hyphenate "instruction set" when it's part of a noun phrase
Andrew Waterman
1
-2
/
+2
2018-05-02
Tweaks to preface
Andrew Waterman
1
-3
/
+3
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