Merge branch 'master' of github.com:riscv/riscv-isa-manual

1 files changed, 13 insertions, 13 deletions

diff --git a/src/preface.tex b/src/preface.tex
index 6105777..f529285 100644
--- a/src/preface.tex
+++ b/src/preface.tex
@@ -70,28 +70,28 @@ The major changes in this version of the document include:
 \item Defined instruction-set categories: {\em standard}, {\em
   reserved}, {\em custom}, {\em non-standard}, and {\em
   non-conforming}.
-\item Removed text implying operation under alternate endianess, as
-  alternate-endianess operation has not yet been defined for RISC-V.
+\item Removed text implying operation under alternate endianness, as
+  alternate-endianness operation has not yet been defined for RISC-V.
 \item Changed description of misaligned load and store behavior to
-  match change that this is now an unprivileged ISA manual not a user
-  ISA manual.  Now allows visible misaligned address traps in
-  execution environment interfaces rather then just mandating
+  reflect that this is now an unprivileged ISA manual, not a user
+  ISA manual.  The specification now allows visible misaligned address
+  traps in execution environment interfaces, rather than just mandating
   invisible handling of misaligned loads and stores in user mode.
-  This behavior was already needed to support definition of the
+  This behavior was already needed to support the definition of the
   classic privileged architecture.  Also, now allow access exceptions
   to be reported for misaligned access that should not be emulated.
-\item FENCE.I moved out of mandatory base and into separate extension,
-  with Zifencei ISA name.  FENCE.I was removed from Linux ABI and is
+\item Moved FENCE.I out of the mandatory base and into a separate extension,
+  with Zifencei ISA name.  FENCE.I was removed from the Linux ABI and is
   problematic in implementations with large incoherent instruction and
-  data caches.  However, it is still the only standard
+  data caches.  However, it remains the only standard
   instruction-fetch coherence mechanism.
-\item Optional FENCE.TSO instruction extension added.
+\item Added optional FENCE.TSO instruction extension.
 \item Removed prohibitions on using RV32E with other extensions.
 \item Removed platform-specific mandates that certain encodings
-  produced illegal instruction exceptions in RV32E and RV64I chapters.
-\item Counter/timer instructions are now not considered part of
+  produce illegal instruction exceptions in RV32E and RV64I chapters.
+\item Counter/timer instructions are now not considered part of the
   mandatory base ISA, and so CSR instructions were moved into separate
-  chapter, with the unprivileged counters into another separate
+  chapter, with the unprivileged counters moved into another separate
   chapter.
 \item Explicitly defined the 16-bit half-precision floating-point
   format for floating-point instructions in the 2-bit {\em fmt field.}