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| author | Andrew Waterman <andrew@sifive.com> | 2022-08-29 12:07:55 -0700 |
|---|---|---|
| committer | Bill Traynor <wmat@riscv.org> | 2022-11-04 14:00:57 -0400 |
| commit | 73b8ce78c6efce48eed548007abff5a87a0044db (patch) | |
| tree | e123c9a9f08462c82ab0faba2bf1a1419a3d1b22 /src/preface.tex | |
| parent | 2c91435e24d6b2a78147e0c3eefe546afd97bd6d (diff) | |
| download | riscv-isa-manual-73b8ce78c6efce48eed548007abff5a87a0044db.zip riscv-isa-manual-73b8ce78c6efce48eed548007abff5a87a0044db.tar.gz riscv-isa-manual-73b8ce78c6efce48eed548007abff5a87a0044db.tar.bz2 | |
Standardize on {\tt pc}, rather than PC
We were using a mix of the two, with a bias towards the former.
Resolves #887
Diffstat (limited to 'src/preface.tex')
| -rw-r--r-- | src/preface.tex | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/preface.tex b/src/preface.tex index 7391877..a9cef65 100644 --- a/src/preface.tex +++ b/src/preface.tex @@ -384,8 +384,8 @@ specification. \item An AMO for fetch-and-XOR (AMOXOR) has been added, and the encoding for AMOSWAP has been changed to make room. \item The AUIPC instruction, which adds a 20-bit upper immediate to - the PC, replaces the RDNPC instruction, which only read the current - PC value. This results in significant savings for position-independent + the {\tt pc}, replaces the RDNPC instruction, which only read the current + {\tt pc} value. This results in significant savings for position-independent code. \item The JAL instruction has now moved to the U-Type format with an explicit destination register, and the J instruction has been |