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| author | Krste Asanovic <krste@eecs.berkeley.edu> | 2018-11-04 11:44:31 -0800 |
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| committer | Krste Asanovic <krste@eecs.berkeley.edu> | 2018-11-04 11:44:31 -0800 |
| commit | 35aee50cea66d6dbbd2614da446ccfcc8ed150d7 (patch) | |
| tree | 7cd231c1b2000cc5154e7c6ea6e9a09e69dc37b0 /src/preface.tex | |
| parent | a93bf5ddd06d5ff0e9c14c2a38a73c310ca9e3b9 (diff) | |
| download | riscv-isa-manual-35aee50cea66d6dbbd2614da446ccfcc8ed150d7.zip riscv-isa-manual-35aee50cea66d6dbbd2614da446ccfcc8ed150d7.tar.gz riscv-isa-manual-35aee50cea66d6dbbd2614da446ccfcc8ed150d7.tar.bz2 | |
Made clear fence.tso is an optional extension
Diffstat (limited to 'src/preface.tex')
| -rw-r--r-- | src/preface.tex | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/preface.tex b/src/preface.tex index 3d0569b..d828748 100644 --- a/src/preface.tex +++ b/src/preface.tex @@ -68,7 +68,7 @@ The major changes in this version of the document include: invisible handling of misaligned loads and stores in user mode. This behavior was already needed to support definition of the classic privileged architecture. -\item FENCE.TSO instruction extension added. +\item Optional FENCE.TSO instruction extension added. \item Removed prohibitions on using RV32E with other extensions. \item Removed platform-specific mandates that certain encodings produced illegal instruction exceptions in RV32E and RV64I chapters. @@ -89,7 +89,7 @@ The major changes in this version of the document include: \item Defined the term IALIGN as shorthand to describe the instruction-address alignment constraint. \end{itemize} -~\\ +\\ \section*{Preface to Document Version 2.2} |