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| author | John Hauser <31252952+jhauser-us@users.noreply.github.com> | 2021-11-15 14:32:47 -0800 |
|---|---|---|
| committer | Bill Traynor <btraynor@gmail.com> | 2022-07-26 11:19:26 -0400 |
| commit | eafaf2a5c24afe3bcc18b75edcdeb0b1db177302 (patch) | |
| tree | b264a9a4395c4f475ba17dec503d0cadc10ce3b5 /src/hypervisor.tex | |
| parent | 5a6eae0ddcfbeceab671a749f94053beaebfe5aa (diff) | |
| download | riscv-isa-manual-eafaf2a5c24afe3bcc18b75edcdeb0b1db177302.zip riscv-isa-manual-eafaf2a5c24afe3bcc18b75edcdeb0b1db177302.tar.gz riscv-isa-manual-eafaf2a5c24afe3bcc18b75edcdeb0b1db177302.tar.bz2 | |
Memory access traps may write zero to stval (#776)
Account for the fact that, once again, memory access traps may write
zero to stval.
Diffstat (limited to 'src/hypervisor.tex')
| -rw-r--r-- | src/hypervisor.tex | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/hypervisor.tex b/src/hypervisor.tex index 357132e..42d0846 100644 --- a/src/hypervisor.tex +++ b/src/hypervisor.tex @@ -342,7 +342,8 @@ a guest virtual address to {\tt stval}, GVA is set to~1. For any other trap into HS-mode, GVA is set to~0. \begin{commentary} -For breakpoint and memory access traps, +For breakpoint and memory access traps +that write a nonzero value to {\tt stval}, GVA is redundant with field SPV (the two bits are set the same) except when the explicit memory access of an HLV, HLVX, or HSV instruction causes a fault. |