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| author | Andrew Waterman <andrew@sifive.com> | 2023-01-30 19:57:37 -0800 |
|---|---|---|
| committer | Bill Traynor <wmat@riscv.org> | 2023-02-28 14:27:21 -0500 |
| commit | 07feb44e8ff74a13520cb2c09086b88dc49817ad (patch) | |
| tree | 976aa021caa03722ddf0261c4dfd743a0dcfae10 /src/hypervisor.tex | |
| parent | c8db45d99d000083c0d85a61b2dd755f250cdbef (diff) | |
| download | riscv-isa-manual-07feb44e8ff74a13520cb2c09086b88dc49817ad.zip riscv-isa-manual-07feb44e8ff74a13520cb2c09086b88dc49817ad.tar.gz riscv-isa-manual-07feb44e8ff74a13520cb2c09086b88dc49817ad.tar.bz2 | |
Clarify WFI trapping behavior (#972)
Resolves #961.
See discusson on that issue for motivation.
Diffstat (limited to 'src/hypervisor.tex')
| -rw-r--r-- | src/hypervisor.tex | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/hypervisor.tex b/src/hypervisor.tex index 8dbec47..4e3fbe5 100644 --- a/src/hypervisor.tex +++ b/src/hypervisor.tex @@ -278,6 +278,9 @@ instruction exception. When VTW=1 (and assuming {\tt mstatus}.TW=0), an attempt in VS-mode to execute WFI raises a virtual instruction exception if the WFI does not complete within an implementation-specific, bounded time limit. +An implementation may have WFI always raise a virtual instruction exception in +VS-mode when VTW=1 (and {\tt mstatus}.TW=0), even if there are pending +globally-disabled interrupts when the instruction is executed. When VTVM=1, an attempt in VS-mode to execute SFENCE.VMA or SINVAL.VMA or to access CSR {\tt satp} raises a virtual instruction exception. |