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| author | John Hauser <31252952+jhauser-us@users.noreply.github.com> | 2021-11-18 13:44:29 -0800 |
|---|---|---|
| committer | Bill Traynor <btraynor@gmail.com> | 2022-07-26 11:19:27 -0400 |
| commit | 3c3f95c23b873e30c1447ecc5587813f2694e3c9 (patch) | |
| tree | 59c0d56b6718b666799b7217141f3098a40e9162 /src/hypervisor.tex | |
| parent | 8d5dd05a9062f1ae2f461d9245e409a47cd324c1 (diff) | |
| download | riscv-isa-manual-3c3f95c23b873e30c1447ecc5587813f2694e3c9.zip riscv-isa-manual-3c3f95c23b873e30c1447ecc5587813f2694e3c9.tar.gz riscv-isa-manual-3c3f95c23b873e30c1447ecc5587813f2694e3c9.tar.bz2 | |
H extension requires page-based address translation (#778)
Diffstat (limited to 'src/hypervisor.tex')
| -rw-r--r-- | src/hypervisor.tex | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/hypervisor.tex b/src/hypervisor.tex index 42d0846..5a9be40 100644 --- a/src/hypervisor.tex +++ b/src/hypervisor.tex @@ -31,7 +31,8 @@ The hypervisor extension depends on an ``I'' base integer ISA with 32 {\tt x} registers (RV32I or RV64I), not RV32E, which has only 16 {\tt x} registers. CSR {\tt mtval} must not be read-only zero, and -{\tt satp}.MODE must not be read-only zero (only Bare). +standard page-based address translation must be supported, either +Sv32 for RV32, or a minimum of Sv39 for RV64. The hypervisor extension is enabled by setting bit 7 in the {\tt misa} CSR, which corresponds to the letter H. |