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2024-06-25Merge up to ad87fbd1cf28760795c4e18f3318a2d720e5a8a6 from upstreamEvgeniy Naydanov4-2/+297
Conflicts: * `doc/openocd.texi`: due to d382c95d57c0ad9ed2dcc83c95404babb7647708, resolved by selecting the upstream version. * `src/server/gdb_server.c`: between 944fe66f104e356c5fcd2b5c25200cebef9b389c and 92e8823ebdb6d01b41bb5d79af49501d525acd1d. Resolved by adopting the use of `LOG_TARGET_*`. * `src/target/target.c`: between 639e68a621b7ae8c4a296ca7e45b47075268fded and c5358c84ad0d3e7497498e0457cec7785f72910a, selected the version from `riscv-openocd`. Change-Id: Ic1327f25e147945e0ec82947a82452501e8ee5de
2024-06-08tcl/target: add nRF53 and nRF91 config filesTomas Vanek3-0/+295
Both devices can be configured with or without SWD multidrop. nRF53 network core is examined on demand to avoid problems when the core is forced off. Change-Id: I08f88ff48ff7ac592e9214b89ca8e5e9428573a5 Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: https://review.openocd.org/c/openocd/+/8113 Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Tested-by: jenkins
2024-06-08tcl/target/c100helper: fix syntax errorsNoah Moroze1-2/+2
Fixes: 64d89d5ee1a5 ("tcl: [3/3] prepare for jimtcl 0.81 'expr' syntax change") These syntax errors were caught by tclint v0.2.5 (https://github.com/nmoroze/tclint): ``` tclint tcl/target/c100helper.tcl | grep "syntax error" ``` Change-Id: I511c54353c4853560adca6b4852d48df2aade283 Signed-off-by: Noah Moroze <noahmoroze@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/8280 Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Tested-by: jenkins
2024-05-30Merge up to 437dde701c13e707e5fd912ef6403e09052e4d9b from upstreamEvgeniy Naydanov2-6/+157
Conflict in src/rtos/FreeRTOS.c due to fbea7d5d38d0dcbdd71cb574da9bd12c78b568cf -- resolved by replacing `target->type->name` with a call to `target_type_name()`. Change-Id: I56702c6133894458903de7a4d764903004aa8b86
2024-05-26tcl/target/nrf52: Configure trace port speedMarc Schink1-0/+20
Configure the TRACECONFIG.TRACEPORTSPEED register depending on the trace clock speed. Also catch invalid trace clock speeds. Change-Id: I1ece1cc59da539732d2d71f296fd55799c195387 Signed-off-by: Marc Schink <dev@zapb.de> Reviewed-on: https://review.openocd.org/c/openocd/+/8256 Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Tested-by: jenkins
2024-05-26tcl/target/nrf52: Use 'error' instead of 'echo'Marc Schink1-6/+3
Use 'error' instead of 'echo' for error messages. Otherwise, capturing is always started, for example with an unsupported device. While at it, make the error messages more consistent and clear. Change-Id: I83c9abfb4514e6b638c4be14651e67f768af8bad Signed-off-by: Marc Schink <dev@zapb.de> Reviewed-on: https://review.openocd.org/c/openocd/+/8255 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-by: <post@frankplowman.com>
2024-05-04tcl/target: Add helpers for booting Xilinx ZynqMP from JTAGSean Anderson1-0/+134
Add some helpers for booting ZynqMPs over JTAG. Normally, the CSU ROM will load boot.bin from the boot medium. However, when booting from JTAG we have to do this ourselves. There are generally two parts to this. First, we need to load the PMU firmware. Xilinx's tools do this by attaching to the PMU (a Microblaze CPU) over JTAG. However, the TAP is undocumented and we don't have any microblaze support in-tree. So instead we do it the same way FSBL does it: - We ask the PMU to halt - We load the firmware into the PMU RAM - We ask the PMU to resume The second thing we need to do is start one of the APU cores. When an APU is released from reset, it starts executing at the value of its RVBARADDR. While we could load the APU firmware over the AXI target, it is faster to load it over the APU target. To do this, we put the APU into an infinite loop before halting it. As an aside, I chose to use the "APU" terminology as opposed to "core" to make it clear that these commands operate on the A53 cores and not the R5F cores. Typical usage of these commands could look something like targets uscale.axi boot_pmu /path/to/pmu-firmware.bin boot_apu /path/to/u-boot-spl.bin But of course there is always the option to call lower-level commands individually if your boot process is more unusual. Signed-off-by: Sean Anderson <sean.anderson@seco.com> Change-Id: I816940c2022ccca0fabb489aa75d682edd0f6138 Reviewed-on: https://review.openocd.org/c/openocd/+/8133 Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Tested-by: jenkins
2024-04-27Merge up to 04154af5d6cd5fe76a2583778379bdacb5aa6fb0 from upstreamEvgeniy Naydanov1-1/+1
Change-Id: I84c1566472e5416bc2a71afa5adaf63c6c7a4a75
2024-04-07zynq_7000.cfg: Fix issue 'Error: can't read "zynq_pl": no such variable'Dominik Wernberger1-1/+1
Change-Id: Ic79ce114b60d0707a6e082a81743b378b164b4e2 Signed-off-by: Dominik Wernberger <dominik.wernberger@gmx.de> Reviewed-on: https://review.openocd.org/c/openocd/+/8190 Reviewed-by: Daniel Anselmi <danselmi@gmx.ch> Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Tested-by: jenkins
2024-03-28Merge up to a35e254c5383008cdacf7838a777f7f17af5eeb1 from upstreamEvgeniy Naydanov1-5/+3
Checkpatch-ignore: MACRO_ARG_REUSE, MACRO_ARG_PRECEDENCE Change-Id: Icd10f44d162054f8f32019a579ccbdda2cee7a91
2024-03-09target/nrf51: use PAN #16 workaround in reset-init onlyTomas Vanek1-1/+1
After 'reset run' or 'reset halt' the loaded application is expected to manipulate RAMON register to workaround the known silicon errata. Moreover, writing to RAMON register from 'reset-end' event after 'reset run' may collide with application intentions. Use the workaround in 'reset-init' event only to ensure correct function of target algorithms. Change-Id: I7d2d92e6805a05a83676edb46b3163ef39b9a7e4 Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: https://review.openocd.org/c/openocd/+/8104 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2024-03-09flash/nor/nrf5, target/nrf51: deprecate nrf51 flash driverTomas Vanek1-4/+2
Use the newer driver name 'nrf5' instead. While on it set the unused parameters of flash bank creation to zero. While on it remove 2 empty comments. Change-Id: I9cf0eadc5b696e6c8b7e6aec0ea3345967523e87 Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: https://review.openocd.org/c/openocd/+/8103 Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Tested-by: jenkins
2024-01-29Merge up to 9659a9b5e28dc615dfb508d301fdd8fa426c191b from upstreamEvgeniy Naydanov5-397/+442
Change-Id: I2fda9689d3465b3d8c8f3459b1ed954cb1d70fdc
2024-01-28target/xtensa: add dual-core supportIan Thompson3-371/+407
- Example for configuring multiple non-SMP Xtensa cores e.g. for heterogeneous debug - JTAG only at this time; DAP out of scope - Dual-Xtensa Palladium example via VDebug - Update Xtensa core config examples Signed-off-by: Ian Thompson <ianst@cadence.com> Change-Id: I6d2b3d13fa8075416dcd383cf256a3e8582ee1c1 Reviewed-on: https://review.openocd.org/c/openocd/+/8078 Tested-by: jenkins Reviewed-by: Jacek Wuwer <jacekmw8@gmail.com> Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2024-01-21jtag/vdebug: add support for DAP6Jacek Wuwer2-26/+35
This change implements the support for the ARM Debug Interface v6. The DAP-level interface properly selects the DP Banks and AP address. Sample ARM configuration DAP and JTAG scripts have been updated. Change-Id: I7df87ef764bca587697c778810443649a7f46c2b Signed-off-by: Jacek Wuwer <jacekmw8@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/8067 Tested-by: jenkins Reviewed-by: Ian Thompson <ianst@cadence.com> Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2024-01-10Merge commit 'adcc8ef87bc1ed47c95f1f2d23072b2b916e1555' into en-sc/from_upstreamEvgeniy Naydanov6-0/+431
Change-Id: I6a718561985acf398ee47cec95c6ee6e24b9c9b7
2024-01-06flash/nor/kinetis: add support for NXP S32K seriesDavid Vidrie Leon1-0/+79
S32K General-Purpose Microcontrollers Scalable, low-power Arm® Cortex®-M series-based microcontrollers AEC-Q100 qualified with advanced safety and security and software support for industrial and automotive ASIL B/D applications in body, zone control, and electrification. Change-Id: I4143258535437c18b81802436267bfd561de9d31 Signed-off-by: David Vidrie Leon <davidvidrie@geotab.com> Reviewed-on: https://review.openocd.org/c/openocd/+/8012 Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Tested-by: jenkins
2023-12-30tcl/target: Add Geehy APM32F1x configMarc Schink1-0/+57
Tested with APM32F103CBT6 using JTAG and SWD transport. All flash operations, including sector and device protection, work as expected. Change-Id: Ibefe1a65d710aea87b86ab7ff8a4153512a0ea4f Signed-off-by: Marc Schink <dev@zapb.de> Reviewed-on: https://review.openocd.org/c/openocd/+/8017 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2023-12-30tcl/target: Add Geehy APM32F4x configMarc Schink1-0/+57
Tested with APM32407RGT6 using JTAG and SWD transport. All flash operations, including sector and device protection, work as expected. Revision identifier (0x0009) is not updated due to missing documentation. Change-Id: I33f4630fd00096656369ecc923aea2dcad77c7d3 Signed-off-by: Marc Schink <dev@zapb.de> Reviewed-on: https://review.openocd.org/c/openocd/+/8016 Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-12-30tcl/target: Add Geehy APM32F0x configMarc Schink1-0/+49
Tested with APM32F030C8T using SWD transport. All flash operations, including sector and device protection, work as expected. Revision identifier (0x0011) is not updated due to missing documentation. Introduce a new directory structure that contains the manufacturer for the sake of clarity. Change-Id: I679387943b09fef640f8f8b6904e542f4e4b29aa Signed-off-by: Marc Schink <dev@zapb.de> Reviewed-on: https://review.openocd.org/c/openocd/+/8015 Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Tested-by: jenkins
2023-12-30tcl/target: add Marvell Octeon TX2 CN9130 targetHenrik Nordström1-0/+178
This has a quite complex JTAG router chain requiring both a custom BYPASS instruction to access child taps, and JTAG configuration to enable individual DAP nodes. Change-Id: I6f5345764e1566d70c8526a7e8ec5d250185bd2c Signed-off-by: Henrik Nordström <henrik.nordstrom@addiva.se> Reviewed-on: https://review.openocd.org/c/openocd/+/8042 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-12-24tcl/target/ti_k3: Add J722S SoCNishanth Menon1-0/+11
Add support for the TI K3 family J722S SoC. This SoC is a variant of AM62P chassis with a different JTAG ID, additional R5 added in (along with C7x and few other peripheral changes). Reuse existing definition. For further details, see https://www.ti.com/lit/zip/sprujb3 Change-Id: I754e6be8df3a26212437ea955f6a791d7c99b0c8 Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-on: https://review.openocd.org/c/openocd/+/8049 Reviewed-by: Bryan Brattlof <hello@bryanbrattlof.com> Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Tested-by: jenkins
2023-12-22Merge commit '16e9b9c44fa62ea6eec99d1fb7bc43a8f1cc2f7e' into from_upstreamTim Newsome2-3/+97
Conflicts: configure.ac tcl/target/gd32vf103.cfg Change-Id: I72bbb973249b7bbfa720696fa2c76a87a41a2e9c
2023-12-10tcl/target/at91sama5d2.cfg: allow choice of SWD instead of JTAGPeter Lawrence1-2/+18
The target supports both SWD and JTAG, but the existing cfg file only supports JTAG. Using the standard [using_jtag] mechanism, the user would now have a choice. Change-Id: Ic6adb68090422812d591f6bf5b945ac10f323c74 Signed-off-by: Peter Lawrence <majbthrd@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/8020 Reviewed-by: Jörg Wunsch <openocd@uriah.heep.sax.de> Reviewed-by: Paul Fertser <fercerpav@gmail.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-12-05Merge commit 'd4575b647a3603200a9bb4a784d170f792ab88d0' into from_upstreamTim Newsome1-30/+87
Change-Id: Iaa299c50b338089f1b3b7ff7d89fad39ac20a7c1
2023-12-05Merge commit 'bcaac692d0fce45189279a4c80cbd6852e4bbf4e' into from_upstreamTim Newsome2-6/+71
Conflicts: src/target/breakpoints.c Change-Id: I815ac06fbe74398fad307112e95fde5c49bbc590
2023-11-30tcl/target/gd32vf103: work around broken ndmresetThomas Hebb1-0/+77
On this chip, the ndmreset bit in the RISC-V debug module doesn't trigger a system reset like it should. To work around this, add a custom "reset-assert" handler in its config file that resets the system by writing to memory-mapped registers. I've tested this workaround on a Sipeed Longan Nano dev board with a GD32VF103CBT6 chip. It works correctly for both "reset run" and "reset halt" (halting at pc=0 for the latter). I originally submitted[1] this workaround to the riscv-openocd fork of OpenOCD. That fork's maintainers accepted it, but have not upstreamed it like they have several other of my changes. [1] https://github.com/riscv/riscv-openocd/pull/538 Change-Id: I7482990755b300fcbe4963c9a599d599bc02684d Signed-off-by: Thomas Hebb <tommyhebb@gmail.com> Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: https://review.openocd.org/c/openocd/+/6957 Tested-by: jenkins Reviewed-by: zapb <dev@zapb.de>
2023-11-27Merge commit '4b1ea8511a7da9d7201df40302e3341c6e97ffdd' into from_upstreamTim Newsome8-11/+235
Change-Id: I59366e08a4ac7e443e426b5fd6727c649f1ac9d5
2023-11-20Merge commit '18281b0c497694d91c5608be54583172838be75c' into from_upstreamTim Newsome2-0/+99
Change-Id: I05cd5ef9b04fa61a27321ae9b6a4fecabe3dee80
2023-11-11tcl/target/ti_k3: Add AM273 SoCNishanth Menon1-0/+21
Add support for the TI K3 family AM273 SoC. For further details, see https://www.ti.com/lit/pdf/spruiu0 Change-Id: Ifa21d0760831f4f525ecd976fb8d086ffdbc9e9f Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-on: https://review.openocd.org/c/openocd/+/7950 Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Tested-by: jenkins
2023-11-11tcl/target/ti_k3: Add AM263 SoCNishanth Menon1-0/+18
Add support for the TI K3 family AM263 SoC. For further details, see https://www.ti.com/lit/pdf/spruim2 Change-Id: I9a91b3d675511661dfc2710a7183bd59b98da133 Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-on: https://review.openocd.org/c/openocd/+/7948 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-11-11tcl/target/ti_k3: Add AM243 SoCNishanth Menon1-0/+9
Add support for the TI K3 family AM243 SoC. This SoC is built on the same base of AM642, so reuse the configuration with the exception of Cortex-A53 which is not available on this device. For further details, see https://www.ti.com/lit/pdf/spruim2 Change-Id: I971ba878b0f503e5120f6853634776eb61d05080 Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-on: https://review.openocd.org/c/openocd/+/7946 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-11-11tcl/target/ti_k3: Sort the SoC documentation alphabeticallyNishanth Menon1-10/+10
Sort the documentation for the TI K3 parts alphabetically. Change-Id: I2c40714ad590e3d9232a6f915c157d677e0c3610 Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-on: https://review.openocd.org/c/openocd/+/7945 Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Tested-by: jenkins
2023-11-11tcl/target/ti_k3: Make Cortex-A processors optionalNishanth Menon1-16/+18
The AM2x family of K3 SoCs typically do not contain a Cortex-A53 or A72 processor. So, make the cpu "up" functions available when armv8 processor count > 0. Change-Id: I985b194fe7cc63e4134ad84ccd921cc456eb412f Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-on: https://review.openocd.org/c/openocd/+/7944 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-11-11tcl/target/ti_k3: Convert memory access ap port num as a variableNishanth Menon1-1/+4
Convert the memory access ap port num as a variable to allow support for the AM2x family of K3 SoCs. Change-Id: Ibd96c94055721f60d95179dab21d014c15b0f562 Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-on: https://review.openocd.org/c/openocd/+/7943 Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Tested-by: jenkins
2023-11-11tcl/target/ti_k3: Convert Cortex-R5 ap port num as a variableNishanth Menon1-2/+3
Convert the Cortex-R5 ap port num as a variable to allow support for the AM2x family of K3 SoCs. Change-Id: I7dc8b459dca8b5f21395230b5cb782b14538bd48 Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-on: https://review.openocd.org/c/openocd/+/7942 Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Tested-by: jenkins
2023-11-11tcl/target/ti_k3: Convert sysctrl ap port num as a variableNishanth Menon1-2/+5
Convert the sysctrl ap port num as a variable to allow support for the AM2x family of K3 SoCs. Change-Id: I1b5b55e48240e6654779dd636fdf07bca055e192 Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-on: https://review.openocd.org/c/openocd/+/7941 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-11-06Merge commit '05ee88915520d1dd82da94a016a9374a1f3a8129' into from_upstreamTim Newsome3-1/+54
Conflicts: src/jtag/drivers/xds110.c src/target/riscv/riscv.c src/target/riscv/riscv_semihosting.c tcl/target/esp_common.cfg Change-Id: If0c02817df03b7fd700cc84b4da2c02d36737d28
2023-10-27Merge commit '9f23a1d7c1e27c556ef9787b9d3f263f5c1ecf24' into from_upstreamTim Newsome12-37/+456
Conflicts: HACKING src/target/riscv/riscv-013.c Change-Id: I43ccb143cae8daa39212d66a8824ae3ad2af6fef
2023-10-23Merge commit 'e17fe4db0f256ee4fb97dcfd6b9f7f55c966b190' into from_upstreamTim Newsome1-8/+13
Conflicts: src/flash/nor/drivers.c src/target/riscv/riscv.c Change-Id: Ide3eded7e0d5b0b446bfd0873a32c00cc9f128bd
2023-10-16Merge commit '0384fe5d596f42388f8b84d42959d899f29388ab' into from_upstreamTim Newsome1-4/+20
Conflicts: .github/workflows/snapshot.yml src/rtos/FreeRTOS.c Change-Id: I4c9ff887b69140e0f61cb3f75a2f2c1a12071320
2023-10-07target/nrf52: Create and configure TPIUFrank Plowman1-0/+49
Firstly, create the TPIU nrf52.tpiu if using the nrf52 target. This is standard, using AP 0 and TPIU base address 0xE0040000. Secondly, add a pre_enable handler for this TPIU which configures the TRACEMUX field of the TRACECONFIG register. This register is reset every time the MCU resets, so the pre_enable handler creates a reset-end handler to ensure the register remains set. Change-Id: I408b20fc03dc2060c21bad0c21ed713eee55a113 Signed-off-by: Frank Plowman <post@frankplowman.com> Reviewed-on: https://review.openocd.org/c/openocd/+/7901 Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Tested-by: jenkins
2023-10-07tcl/target/ti_k3: Add AXI-AP port for direct SoC memory map accessNishanth Menon1-0/+3
While we can read and write from memory from the view of various processors, all K3 debug systems have a AXI Access port that allows us to directly access memory from debug interface. This port is especially useful in the following scenarios: 1. Debug cache related behavior on processors as this provides a direct bypass path. 2. Processor has crashed or inaccessible for some reason (low power state etc.) 3. Scenarios prior to the processor getting active. 4. Debug MMU or address translation issues (example: TI's Region Address Table {RAT} translation table used to physically map SoC address space into R5/M4F processor address space) The AXI-AP port is the same for all processors in TI's K3 family. To prevent a circular-loop scenario for axi-ap accessing debug memory with dmem (direct memory access debug), enable this only when dmem is disabled. Change-Id: Ie4ca9222f034ffc2fa669fb5124a5f8e37b65e3b Reported-by: Dubravko Srsan <dubravko.srsan@dolotron.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-on: https://review.openocd.org/c/openocd/+/7899 Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Tested-by: jenkins
2023-10-07tcl/target/ti_k3: Introduce RTOS array variable to set various CPU RTOSesNishanth Menon1-4/+17
The Texas Instruments' K3 devices are a mix of AMP and SMP systems. The operating systems used on these processors can vary dramatically as well. Introduce a RTOS array variable, which is keyed off the cpu to identify which RTOS is used on that CPU. This can be "auto" or "hwthread" in case of SMP debug etc. For example: AM625 with an general purpose M4F running Zephyr and 4 A53s running SMP Linux could be invoked by: openocd -c 'set V8_SMP_DEBUG 1' -c 'set RTOS(am625.cpu.gp_mcu) Zephyr' \ -c "set RTOS(am625.cpu.a53.0) hwthread" -f board/ti_am625evm.cfg Change-Id: Ib5e59fa2583b3115e5799658afcdd0ee91935e82 Reported-by: Dubravko Srsan <dubravko.srsan@dolotron.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-on: https://review.openocd.org/c/openocd/+/7898 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-10-07tcl/target/ti_k3: Add coreid identification to SMP processorsDubravko Srsan1-1/+1
Describe the SMP Armv8 cores in SMP configuration with coreid explicitly called out. This allows for gdb session to call the smp behavior clearly. Change-Id: Ie43be22db64737bbb66181f09d3c83567044f3ac Signed-off-by: Dubravko Srsan <dubravko.srsan@dolotron.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-on: https://review.openocd.org/c/openocd/+/7897 Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Tested-by: jenkins
2023-10-07tcl/target/ti_k3: Fix smp target descriptionDubravko Srsan1-1/+1
When _v8_smp_targets is used with V8_SMP_DEBUG=1, describe the targets as SMP targets. However, the variable expansion is not in the context of a proc, and a typo in referring to global $_v8_smp_targets causes this to fail. Just refer to $_v8_smp_targets directly. Change-Id: Iffe5fd2703bed6a9c840284285e70b8a8ce84e17 Signed-off-by: Dubravko Srsan <dubravko.srsan@dolotron.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-on: https://review.openocd.org/c/openocd/+/7896 Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Tested-by: jenkins
2023-09-23tcl/target: add support for Cavium Octeon II CN61xxPeter Mamonov1-0/+15
Change-Id: Ia14854bc64f5a31b6591be69be4edee9cd1310c3 Signed-off-by: Peter Mamonov <pmamonov@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/5249 Reviewed-by: Oleksij Rempel <linux@rempel-privat.de> Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Tested-by: jenkins
2023-09-23tcl/target: Add XLP3xx configuration filesPeter Mamonov4-0/+60
The patch adds configuration files for the following XLP 300-series processors: XLP304, XLP308, XLP316. Change-Id: Iaf2b807abf9fc4d7b51222fd40bdb18c6aca7d9c Signed-off-by: Aleksey Kuleshov <rndfax@yandex.ru> Signed-off-by: Peter Mamonov <pmamonov@gmail.com> CC: Antony Pavlov <antonynpavlov@gmail.com> CC: Dongxue Zhang <elta.era@gmail.com> CC: Oleksij Rempel <linux@rempel-privat.de> CC: Paul Fertser <fercerpav@gmail.com> CC: Salvador Arroyo <sarroyofdez@yahoo.es> CC: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: https://review.openocd.org/c/openocd/+/2323 Tested-by: jenkins Reviewed-by: Oleksij Rempel <linux@rempel-privat.de> Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-09-23tcl/target/ti_k3: Add AM62P SoCNishanth Menon1-2/+11
Add support for the TI K3 family AM62P SoC. This SoC is built on the same base of AM62A7, so reuse the configuration with the exception of the JTAG ID and the actual name used for the R5 core (moved from main domain to wakeup domain). For further details, see https://www.ti.com/lit/pdf/spruj83 Signed-off-by: Nishanth Menon <nm@ti.com> Change-Id: I3a80be9e71204ed7697e51ac1ad488ef405744ef Reviewed-on: https://review.openocd.org/c/openocd/+/7892 Reviewed-by: Bryan Brattlof <hello@bryanbrattlof.com> Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Tested-by: jenkins
2023-09-23tcl/target/ti_k3: Add J784s4 SoCNishanth Menon1-0/+33
Add support for the TI K3 family J784S4/AM69 SoC. For further details, see http://www.ti.com/lit/zip/spruj52 Signed-off-by: Nishanth Menon <nm@ti.com> Change-Id: I3c899aed0cb79ab8bbf8077ca6dfe0636cf72288 Reviewed-on: https://review.openocd.org/c/openocd/+/7890 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
generated by cgit v1.1 at 2024-07-27 19:00:30 +0000