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author | Jacek Wuwer <jacekmw8@gmail.com> | 2024-01-09 14:57:29 +0100 |
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committer | Antonio Borneo <borneo.antonio@gmail.com> | 2024-01-21 21:31:37 +0000 |
commit | 151b743714382120dbe0dee0e0eeb75826ef5b3a (patch) | |
tree | 6d1dd39b2608da1ce747c41e65e2bc53c40ad687 /tcl/target | |
parent | 80b970bd29093a1e3e3b5fdeacda4958721a5afd (diff) | |
download | riscv-openocd-151b743714382120dbe0dee0e0eeb75826ef5b3a.zip riscv-openocd-151b743714382120dbe0dee0e0eeb75826ef5b3a.tar.gz riscv-openocd-151b743714382120dbe0dee0e0eeb75826ef5b3a.tar.bz2 |
jtag/vdebug: add support for DAP6
This change implements the support for the ARM Debug Interface v6.
The DAP-level interface properly selects the DP Banks and AP address.
Sample ARM configuration DAP and JTAG scripts have been updated.
Change-Id: I7df87ef764bca587697c778810443649a7f46c2b
Signed-off-by: Jacek Wuwer <jacekmw8@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8067
Tested-by: jenkins
Reviewed-by: Ian Thompson <ianst@cadence.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Diffstat (limited to 'tcl/target')
-rw-r--r-- | tcl/target/vd_aarch64.cfg | 50 | ||||
-rw-r--r-- | tcl/target/vd_cortex_m.cfg | 11 |
2 files changed, 35 insertions, 26 deletions
diff --git a/tcl/target/vd_aarch64.cfg b/tcl/target/vd_aarch64.cfg index 619134a..177416b 100644 --- a/tcl/target/vd_aarch64.cfg +++ b/tcl/target/vd_aarch64.cfg @@ -2,36 +2,44 @@ # Cadence virtual debug interface # Arm v8 64b Cortex A -if {![info exists _CORES]} { - set _CORES 1 +if {![info exists CORES]} { + set CORES 1 } -if {![info exists _CHIPNAME]} { - set _CHIPNAME aarch64 +if {![info exists CHIPNAME]} { + set CHIPNAME aarch64 +} +if {[info exists ACCESSPORT]} { + set _APNUM "-ap-num $ACCESSPORT" + if { $ACCESSPORT > 0xff } { + set _DAP6 "-adiv6" + } else { + set _DAP6 "-adiv5" + } +} else { + set _APNUM "" } -set _TARGETNAME $_CHIPNAME.cpu -set _CTINAME $_CHIPNAME.cti -set DBGBASE {0x80810000 0x80910000} -set CTIBASE {0x80820000 0x80920000} +set _TARGETNAME $CHIPNAME.cpu +set _CTINAME $CHIPNAME.cti +set _DAPNAME $CHIPNAME.dap -dap create $_CHIPNAME.dap -chain-position $_TARGETNAME -$_CHIPNAME.dap apsel 1 +dap create $_DAPNAME $_DAP6 -chain-position $_TARGETNAME -for { set _core 0 } { $_core < $_CORES } { incr _core } \ +for { set _core 0 } { $_core < $CORES } { incr _core } \ { - cti create $_CTINAME.$_core -dap $_CHIPNAME.dap -ap-num 1 -baseaddr [lindex $CTIBASE $_core] - set _command "target create $_TARGETNAME.$_core aarch64 -dap $_CHIPNAME.dap \ - -dbgbase [lindex $DBGBASE $_core] -cti $_CTINAME.$_core -coreid $_core" + set _cmd "cti create $_CTINAME.$_core -dap $_DAPNAME $_APNUM -baseaddr [lindex $CTIBASE $_core]" + eval $_cmd + set _cmd "target create $_TARGETNAME.$_core aarch64 -dap $_DAPNAME $_APNUM -dbgbase [lindex $DBGBASE $_core] -cti $_CTINAME.$_core -coreid $_core" if { $_core != 0 } { # non-boot core examination may fail - set _command "$_command -defer-examine" - set _smp_command "$_smp_command $_TARGETNAME.$_core" + set _cmd "$_cmd -defer-examine" + set _smp_cmd "$_smp_cmd $_TARGETNAME.$_core" } else { - set _smp_command "target smp $_TARGETNAME.$_core" + set _smp_cmd "target smp $_TARGETNAME.$_core" } - eval $_command + eval $_cmd } -eval $_smp_command +eval $_smp_cmd -# default target is core 0 -targets $_TARGETNAME.0 +set _TARGETCUR $_TARGETNAME.0 +targets $_TARGETCUR diff --git a/tcl/target/vd_cortex_m.cfg b/tcl/target/vd_cortex_m.cfg index 4d7b0df..7db9d3a 100644 --- a/tcl/target/vd_cortex_m.cfg +++ b/tcl/target/vd_cortex_m.cfg @@ -2,11 +2,12 @@ # Cadence virtual debug interface # ARM Cortex M -if {![info exists _CHIPNAME]} { - set _CHIPNAME cortex_m +if {![info exists CHIPNAME]} { + set CHIPNAME cortex_m } -set _TARGETNAME $_CHIPNAME.cpu +set _TARGETNAME $CHIPNAME.cpu +set _DAPNAME $CHIPNAME.dap -dap create $_CHIPNAME.dap -chain-position $_TARGETNAME +dap create $_DAPNAME -chain-position $_TARGETNAME -target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap +target create $_TARGETNAME cortex_m -dap $_DAPNAME |