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| author | Nishanth Menon <nm@ti.com> | 2023-09-06 07:59:23 -0500 |
|---|---|---|
| committer | Antonio Borneo <borneo.antonio@gmail.com> | 2023-09-23 14:32:12 +0000 |
| commit | d2f86dfd05230931fc56a412a6cf5f6265b8562b (patch) | |
| tree | 1302ebe8b7b02d70dfa0b13929726b1a6e50bbe3 /tcl/target | |
| parent | db1bbbf6a446df78a5da50199e209f83fd278c8d (diff) | |
| download | riscv-openocd-d2f86dfd05230931fc56a412a6cf5f6265b8562b.zip riscv-openocd-d2f86dfd05230931fc56a412a6cf5f6265b8562b.tar.gz riscv-openocd-d2f86dfd05230931fc56a412a6cf5f6265b8562b.tar.bz2 | |
tcl/target/ti_k3: Add J784s4 SoC
Add support for the TI K3 family J784S4/AM69 SoC.
For further details, see http://www.ti.com/lit/zip/spruj52
Signed-off-by: Nishanth Menon <nm@ti.com>
Change-Id: I3c899aed0cb79ab8bbf8077ca6dfe0636cf72288
Reviewed-on: https://review.openocd.org/c/openocd/+/7890
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Diffstat (limited to 'tcl/target')
| -rw-r--r-- | tcl/target/ti_k3.cfg | 33 |
1 files changed, 33 insertions, 0 deletions
diff --git a/tcl/target/ti_k3.cfg b/tcl/target/ti_k3.cfg index ffba478..beb98ed 100644 --- a/tcl/target/ti_k3.cfg +++ b/tcl/target/ti_k3.cfg @@ -10,6 +10,8 @@ # Has 2 ARMV8 Cores and 4 R5 Cores and an M3 # * J721S2: https://www.ti.com/lit/pdf/spruj28 # Has 2 ARMV8 Cores and 6 R5 Cores and an M4F +# * J784S4/AM69: http://www.ti.com/lit/zip/spruj52 +# Has 8 ARMV8 Cores and 8 R5 Cores # * AM642: https://www.ti.com/lit/pdf/spruim2 # Has 2 ARMV8 Cores and 4 R5 Cores, M4F and an M3 # * AM625: https://www.ti.com/lit/pdf/spruiv7a @@ -201,6 +203,37 @@ switch $_soc { set _gp_mcu_cores 1 set _gp_mcu_ap_unlock_offsets {0xf0 0x7c} } + j784s4 { + set _K3_DAP_TAPID 0x0bb8002f + + # j784s4 has 2 cluster of 4 A72 cores each. + set _armv8_cpu_name a72 + set _armv8_cores 8 + set ARMV8_DBGBASE {0x90410000 0x90510000 0x90610000 0x90710000 + 0x90810000 0x90910000 0x90a10000 0x90b10000} + set ARMV8_CTIBASE {0x90420000 0x90520000 0x90620000 0x90720000 + 0x90820000 0x90920000 0x90a20000 0x90b20000} + + # J721s2 has 4 clusters of 2 R5 cores each. + set _r5_cores 8 + set R5_DBGBASE {0x9d010000 0x9d012000 + 0x9d410000 0x9d412000 + 0x9d510000 0x9d512000 + 0x9d610000 0x9d612000} + set R5_CTIBASE {0x9d018000 0x9d019000 + 0x9d418000 0x9d419000 + 0x9d518000 0x9d519000 + 0x9d618000 0x9d619000} + set R5_NAMES {mcu_r5.0 mcu_r5.1 + main0_r5.0 main0_r5.1 + main1_r5.0 main1_r5.1 + main2_r5.0 main2_r5.1} + + # sysctrl CTI base + set CM3_CTIBASE {0x20001000} + # Sysctrl power-ap unlock offsets + set _sysctrl_ap_unlock_offsets {0xf0 0x78} + } default { echo "'$_soc' is invalid!" } |