riscv-tools/riscv-openocd.git - Unnamed repository; edit this file 'description' to name the repository.

Branch	Commit message	Author	Age
examine_unavailable_harts	Handling harts becoming available when halted	cgsfv	6 weeks
examine_unavailable_harts_backup	Handle unavailability when deasserting reset	cgsfv	8 weeks
examine_unavailable_harts_rebase	Improved handling of unavailable cores	cgsfv	6 weeks
examine_unavailable_harts_squash	Improved handling of unavailable harts	cgsfv	6 weeks
hypervisor_translate	target/riscv: Support VS-stage and G-stage address translation.	Tim Newsome	14 months
remove-slot_t-from-riscv-013	riscv-013: Remove unused typedef slot_t	Jan Matyas	3 weeks
reset_test	DMI read before asserting ndmreset/haltreq.	Tim Newsome	9 months
riscv	Merge pull request #1089 from en-sc/en-sc/batch-select-dmi	Anatoly Parshintsev	3 days
riscv-batch-cleanup	Fixes of review findings	Jan Matyas	4 months
us_xds110	jtag/drivers/xds110: Fix compiler warning.	Tim Newsome	11 months
[...]

Tag	Download	Author	Age
latest	riscv-openocd-latest.zip riscv-openocd-latest.tar.gz riscv-openocd-latest.tar.bz2	Anatoly Parshintsev	3 days
openocd64-ad4c3e1	riscv-openocd-openocd64-ad4c3e1.zip riscv-openocd-openocd64-ad4c3e1.tar.gz riscv-openocd-openocd64-ad4c3e1.tar.bz2	Tim Newsome	15 months
openocd64-8b80fe1	riscv-openocd-openocd64-8b80fe1.zip riscv-openocd-openocd64-8b80fe1.tar.gz riscv-openocd-openocd64-8b80fe1.tar.bz2	Tim Newsome	15 months
openocd64-41b9c69e92d9660cb2eff508f3bc8218a3b3e461	riscv-openocd-openocd64-41b9c69e92d9660cb2eff508f3bc8218a3b3e461.zip riscv-openocd-openocd64-41b9c69e92d9660cb2eff508f3bc8218a3b3e461.tar.gz riscv-openocd-openocd64-41b9c69e92d9660cb2eff508f3bc8218a3b3e461.tar.bz2	Tim Newsome	15 months
openocd64-d486b21	riscv-openocd-openocd64-d486b21.zip riscv-openocd-openocd64-d486b21.tar.gz riscv-openocd-openocd64-d486b21.tar.bz2	Tim Newsome	15 months
v2018.12.0	riscv-openocd-2018.12.0.zip riscv-openocd-2018.12.0.tar.gz riscv-openocd-2018.12.0.tar.bz2	Tim Newsome	6 years
v20181030	riscv-openocd-20181030.zip riscv-openocd-20181030.tar.gz riscv-openocd-20181030.tar.bz2	Tim Newsome	6 years
v20180928	riscv-openocd-20180928.zip riscv-openocd-20180928.tar.gz riscv-openocd-20180928.tar.bz2	cgsfv	6 years
v20180629	riscv-openocd-20180629.zip riscv-openocd-20180629.tar.gz riscv-openocd-20180629.tar.bz2	Palmer Dabbelt	6 years
v20171231	riscv-openocd-20171231.zip riscv-openocd-20171231.tar.gz riscv-openocd-20171231.tar.bz2	Palmer Dabbelt	6 years
[...]

Age	Commit message	Author	Files	Lines
3 days	Merge pull request #1089 from en-sc/en-sc/batch-select-dmiHEAD latest riscv	Anatoly Parshintsev	1	-0/+2
7 days	target/riscv: select DMI IR on batch access.	Evgeniy Naydanov	1	-0/+2
11 days	Merge pull request #1073 from en-sc/en-sc/abs-reg-batch	Evgeniy Naydanov	3	-100/+308
13 days	Merge pull request #1044 from en-sc/en-sc/riscv-011-sep-reg-acc	Evgeniy Naydanov	2	-18/+102
2024-06-06	target/riscv: write registers using batch	Evgeniy Naydanov	3	-100/+308
2024-06-05	Merge pull request #1075 from en-sc/en-sc/from_upstream	Evgeniy Naydanov	38	-244/+470
2024-06-04	target/riscv: stop using register_get/set for 0.11 targets	Evgeniy Naydanov	2	-16/+102
2024-06-04	Revert "Initialize all registers in examine"	Evgeniy Naydanov	1	-2/+0
2024-06-04	Merge pull request #1056 from aap-sc/aap-sc/no_hit_bit_status	Anatoly Parshintsev	2	-15/+90
2024-06-04	Merge pull request #1077 from riscv-collab/remove-slot_t-from-riscv-013	Evgeniy Naydanov	1	-6/+0
[...]