diff options
author | Nishanth Menon <nm@ti.com> | 2023-10-17 13:51:51 -0500 |
---|---|---|
committer | Antonio Borneo <borneo.antonio@gmail.com> | 2023-11-11 18:44:10 +0000 |
commit | 00b07390826f7cd5f72bc036e3907a87c6cbc33d (patch) | |
tree | 11fef55d4e94a24f2078641ceb988d6316d63eba /tcl/target | |
parent | 42441fd96cf86ffca61f77afe24aae21fb00bb89 (diff) | |
download | riscv-openocd-00b07390826f7cd5f72bc036e3907a87c6cbc33d.zip riscv-openocd-00b07390826f7cd5f72bc036e3907a87c6cbc33d.tar.gz riscv-openocd-00b07390826f7cd5f72bc036e3907a87c6cbc33d.tar.bz2 |
tcl/target/ti_k3: Convert sysctrl ap port num as a variable
Convert the sysctrl ap port num as a variable to allow support for the
AM2x family of K3 SoCs.
Change-Id: I1b5b55e48240e6654779dd636fdf07bca055e192
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7941
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Diffstat (limited to 'tcl/target')
-rw-r--r-- | tcl/target/ti_k3.cfg | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/tcl/target/ti_k3.cfg b/tcl/target/ti_k3.cfg index 1cd85ee..78ee8b2 100644 --- a/tcl/target/ti_k3.cfg +++ b/tcl/target/ti_k3.cfg @@ -44,6 +44,7 @@ set CM3_CTIBASE {0x3C016000} # sysctrl power-ap unlock offsets set _sysctrl_ap_unlock_offsets {0xf0 0x44} +set _sysctrl_ap_num 7 # All the ARMV8s are the next processors. # CL0,CORE0 CL0,CORE1 CL1,CORE0 CL1,CORE1 @@ -266,9 +267,11 @@ set _TARGETNAME $_CHIPNAME.cpu set _CTINAME $_CHIPNAME.cti # sysctrl is always present -cti create $_CTINAME.sysctrl -dap $_CHIPNAME.dap -ap-num 7 -baseaddr [lindex $CM3_CTIBASE 0] +cti create $_CTINAME.sysctrl -dap $_CHIPNAME.dap \ + -ap-num $_sysctrl_ap_num -baseaddr [lindex $CM3_CTIBASE 0] -target create $_TARGETNAME.sysctrl cortex_m -dap $_CHIPNAME.dap -ap-num 7 -defer-examine \ +target create $_TARGETNAME.sysctrl cortex_m -dap $_CHIPNAME.dap \ + -ap-num $_sysctrl_ap_num -defer-examine \ -rtos [_get_rtos_type_for_cpu $_TARGETNAME.sysctrl] $_TARGETNAME.sysctrl configure -event reset-assert { } |