aboutsummaryrefslogtreecommitdiff
path: root/riscv/triggers.cc
AgeCommit message (Expand)AuthorFilesLines
2022-12-21triggers: add mcontrol6 triggerYenHaoChen1-0/+46
2022-12-21triggers: refactor: add mcontrol_common_t::legalize_match() functionYenHaoChen1-14/+16
2022-12-21triggers: refactor: remove redundant namespace qualifiersYenHaoChen1-7/+7
2022-12-21triggers: refactor: extract mcontrol_common_t from mcontrol_tYenHaoChen1-2/+2
2022-12-21triggers: refactor: update trigger_t::mode_match()YenHaoChen1-5/+5
2022-12-21triggers: refactor: add trigger_t::mode_match() functionYenHaoChen1-14/+13
2022-12-21triggers: refactor: add mcontrol.vs and mcontrol.vuYenHaoChen1-3/+2
2022-12-21triggers: refactor: cleaner vs and vu checkingYenHaoChen1-8/+4
2022-12-10Move mhselect_compare into mhselect_interpretationScott Johnson1-2/+2
2022-12-10Use interpret_mhselect() to decide textra compare modeScott Johnson1-16/+2
2022-12-10Interpret mhselect in centralized placeScott Johnson1-12/+2
2022-12-10triggers: add mcontext and hcontext CSRsYenHaoChen1-7/+11
2022-12-10triggers: add scontext CSRYenHaoChen1-2/+10
2022-12-10triggers: checking textra (tdata3); checking ASID and VMIDYenHaoChen1-2/+46
2022-12-09triggers: implement tdata3 CSR fieldsYenHaoChen1-0/+59
2022-12-09refactor: remove proc parameter from functions of module_tYenHaoChen1-5/+5
2022-12-01Remove unused constructor arg from match_result_tScott Johnson1-3/+3
2022-12-01Use std::optional for detect_trap_match in trigger_t hierarchyScott Johnson1-8/+8
2022-12-01Convert triggers::module_t::detect_trap_match to std::optionalScott Johnson1-3/+3
2022-12-01Remove unnecessary logical-orScott Johnson1-1/+1
2022-12-01Use std::optional for detect_memory_access_match in trigger_t hierarchyScott Johnson1-7/+7
2022-12-01Convert triggers::module_t::detect_memory_access_match to std::optionalScott Johnson1-3/+3
2022-12-01Extract common method for legalizing trigger action fieldScott Johnson1-9/+7
2022-12-01Add noexcept to trigger-matching functionsScott Johnson1-5/+5
2022-12-01Move tdata2 into parent classScott Johnson1-2/+2
2022-12-01triggers: s and u of mcontrol dependents on extension supportYenHaoChen1-2/+2
2022-12-01triggers: legalize mcontrol.actionYenHaoChen1-0/+2
2022-12-01triggers: refactor: rename memory_access_match() to detect_memory_access_match()YenHaoChen1-4/+4
2022-12-01triggers: add etrigger_tYenHaoChen1-1/+60
2022-12-01triggers: add itrigger_tYenHaoChen1-1/+73
2022-12-01triggers: hardware should ignore writes that set dmode to 1 if the previous t...YenHaoChen1-0/+4
2022-12-01triggers: hardware must zero chain in writes that set dmode to 0 if the next ...YenHaoChen1-4/+7
2022-11-30triggers: refactor: remove obsolete checking of debug_mode in disabled_trigge...YenHaoChen1-1/+1
2022-11-30triggers: refactor: use CSR_MCONTROL_DMODE(xlen) instead of MCONTROL_DMODE(xlen)YenHaoChen1-3/+3
2022-11-30triggers: dmode only writable from debug modeYenHaoChen1-0/+6
2022-11-30triggers: refactor: use modern C++ loopYenHaoChen1-5/+5
2022-11-30triggers: refactor: reorder functions in module_t for consistencyYenHaoChen1-29/+29
2022-11-30triggers: make disabled_trigger_t as default triggerYenHaoChen1-1/+1
2022-11-30triggers: refactor: use CSR_TDATA1_TYPE_MCONTROL instead of MCONTROL_TYPE_MAT...YenHaoChen1-2/+2
2022-11-30triggers: refactor: add assertions for mcontrol.type checkingYenHaoChen1-0/+1
2022-11-30triggers: add disabled_trigger_tYenHaoChen1-2/+32
2022-11-30triggers: mcontrol does not support VS and VU modesYenHaoChen1-1/+2
2022-11-30triggers: refactor: remove return value of mcontrol_t::tdata1_write(...) and ...YenHaoChen1-8/+6
2022-11-30triggers: refactor: move dmode checking of tdata2 to module_t for consistencyYenHaoChen1-3/+3
2022-11-30triggers: refactor: let action be part of match_result_tYenHaoChen1-5/+3
2022-11-30triggers: refactor: let match_result_t be a struct with fire and timing varia...YenHaoChen1-11/+8
2022-11-29triggers: Access action bit through get_action()Tim Newsome1-1/+1
2022-11-29triggers: rename chainTim Newsome1-5/+5
2022-11-29triggers: refactor: move dmode checking of tdata1 to module_tYenHaoChen1-3/+3
2022-11-29triggers: Rename/move dmodeTim Newsome1-2/+2