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| author | YenHaoChen <howard25336284@gmail.com> | 2022-12-14 20:39:43 +0800 |
|---|---|---|
| committer | YenHaoChen <howard25336284@gmail.com> | 2022-12-21 13:13:38 +0800 |
| commit | ae016f835c4ac8d500935bca472697582acf5e7d (patch) | |
| tree | b9f92efb9471bdf3bd114c01339395d394bbcad8 /riscv/triggers.cc | |
| parent | 5f85e8fac059af40e40b3232cb3c409366c1a38c (diff) | |
| download | riscv-isa-sim-ae016f835c4ac8d500935bca472697582acf5e7d.zip riscv-isa-sim-ae016f835c4ac8d500935bca472697582acf5e7d.tar.gz riscv-isa-sim-ae016f835c4ac8d500935bca472697582acf5e7d.tar.bz2 | |
triggers: refactor: add mcontrol.vs and mcontrol.vu
Diffstat (limited to 'riscv/triggers.cc')
| -rw-r--r-- | riscv/triggers.cc | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/riscv/triggers.cc b/riscv/triggers.cc index 68f11f0..571bcb9 100644 --- a/riscv/triggers.cc +++ b/riscv/triggers.cc @@ -195,9 +195,8 @@ std::optional<match_result_t> mcontrol_t::detect_memory_access_match(processor_t (operation == triggers::OPERATION_STORE && !store) || (operation == triggers::OPERATION_LOAD && !load) || (state->prv == PRV_M && !m) || - (state->prv == PRV_S && !s) || - (state->prv == PRV_U && !u) || - (state->v)) { + (state->prv == PRV_S && !(state->v ? vs : s)) || + (state->prv == PRV_U && !(state->v ? vu : u))) { return std::nullopt; } |