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| author | Tim Newsome <tim@sifive.com> | 2022-11-15 09:58:07 -0800 |
|---|---|---|
| committer | YenHaoChen <howard25336284@gmail.com> | 2022-11-29 07:47:54 +0800 |
| commit | 5d51920dee4a9771ac5d7d978330bb10ad084a3a (patch) | |
| tree | fdf2a2983bf0af1101e34f22dda913678fc71814 /riscv/triggers.cc | |
| parent | 3aec432e12c4d306326d59adbe26cd7b88c686da (diff) | |
| download | riscv-isa-sim-5d51920dee4a9771ac5d7d978330bb10ad084a3a.zip riscv-isa-sim-5d51920dee4a9771ac5d7d978330bb10ad084a3a.tar.gz riscv-isa-sim-5d51920dee4a9771ac5d7d978330bb10ad084a3a.tar.bz2 | |
triggers: Rename/move dmode
dmode() -> get_dmode()
trigger_t.dmode_bit -> mcontrol_t.dmode
Diffstat (limited to 'riscv/triggers.cc')
| -rw-r--r-- | riscv/triggers.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/riscv/triggers.cc b/riscv/triggers.cc index 6c03c9e..6823615 100644 --- a/riscv/triggers.cc +++ b/riscv/triggers.cc @@ -10,7 +10,7 @@ reg_t trigger_with_tdata2_t::tdata2_read(const processor_t UNUSED * const proc) } bool trigger_with_tdata2_t::tdata2_write(processor_t UNUSED * const proc, const reg_t UNUSED val) noexcept { - if (dmode && !proc->get_state()->debug_mode) { + if (get_dmode() && !proc->get_state()->debug_mode) { return false; } tdata2 = val; @@ -39,7 +39,7 @@ reg_t mcontrol_t::tdata1_read(const processor_t * const proc) const noexcept { } bool mcontrol_t::tdata1_write(processor_t * const proc, const reg_t val) noexcept { - if (dmode && !proc->get_state()->debug_mode) { + if (get_dmode() && !proc->get_state()->debug_mode) { return false; } auto xlen = proc->get_xlen(); |