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author | YenHaoChen <howard25336284@gmail.com> | 2022-12-01 10:41:45 +0800 |
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committer | YenHaoChen <howard25336284@gmail.com> | 2022-12-01 10:41:45 +0800 |
commit | 7d05c347567313396c39ff6c5793a68c0290db91 (patch) | |
tree | b1bff39008ab646553e4229e9bc59c95fea1ed80 /riscv/triggers.cc | |
parent | 7965f25acb4fbf99817c1a5c3aef0ce1843b6bc5 (diff) | |
download | riscv-isa-sim-7d05c347567313396c39ff6c5793a68c0290db91.zip riscv-isa-sim-7d05c347567313396c39ff6c5793a68c0290db91.tar.gz riscv-isa-sim-7d05c347567313396c39ff6c5793a68c0290db91.tar.bz2 |
triggers: s and u of mcontrol dependents on extension support
Diffstat (limited to 'riscv/triggers.cc')
-rw-r--r-- | riscv/triggers.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/riscv/triggers.cc b/riscv/triggers.cc index 2e3a4a1..277dd67 100644 --- a/riscv/triggers.cc +++ b/riscv/triggers.cc @@ -76,8 +76,8 @@ void mcontrol_t::tdata1_write(processor_t * const proc, const reg_t val, const b break; } m = get_field(val, MCONTROL_M); - s = get_field(val, MCONTROL_S); - u = get_field(val, MCONTROL_U); + s = proc->extension_enabled_const('S') ? get_field(val, CSR_MCONTROL_S) : 0; + u = proc->extension_enabled_const('U') ? get_field(val, CSR_MCONTROL_U) : 0; execute = get_field(val, MCONTROL_EXECUTE); store = get_field(val, MCONTROL_STORE); load = get_field(val, MCONTROL_LOAD); |