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| author | YenHaoChen <howard25336284@gmail.com> | 2022-11-16 11:51:13 +0800 |
|---|---|---|
| committer | YenHaoChen <howard25336284@gmail.com> | 2022-11-30 12:11:42 +0800 |
| commit | 67e6112b03ee9f91dd5cf901a328d6531ab112a6 (patch) | |
| tree | 1014208841c54d6bdadcb20ebbf405efcbe090e7 /riscv/triggers.cc | |
| parent | a399d65d9fab4c38839a71dbd38d3c04c3494514 (diff) | |
| download | riscv-isa-sim-67e6112b03ee9f91dd5cf901a328d6531ab112a6.zip riscv-isa-sim-67e6112b03ee9f91dd5cf901a328d6531ab112a6.tar.gz riscv-isa-sim-67e6112b03ee9f91dd5cf901a328d6531ab112a6.tar.bz2 | |
triggers: refactor: move dmode checking of tdata2 to module_t for consistency
Diffstat (limited to 'riscv/triggers.cc')
| -rw-r--r-- | riscv/triggers.cc | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/riscv/triggers.cc b/riscv/triggers.cc index 094c4e6..a44b3a8 100644 --- a/riscv/triggers.cc +++ b/riscv/triggers.cc @@ -10,9 +10,6 @@ reg_t trigger_with_tdata2_t::tdata2_read(const processor_t UNUSED * const proc) } bool trigger_with_tdata2_t::tdata2_write(processor_t UNUSED * const proc, const reg_t UNUSED val) noexcept { - if (get_dmode() && !proc->get_state()->debug_mode) { - return false; - } tdata2 = val; return true; } @@ -198,6 +195,9 @@ reg_t module_t::tdata2_read(const processor_t * const proc, unsigned index) cons bool module_t::tdata2_write(processor_t * const proc, unsigned index, const reg_t val) noexcept { + if (triggers[index]->get_dmode() && !proc->get_state()->debug_mode) { + return false; + } bool result = triggers[index]->tdata2_write(proc, val); proc->trigger_updated(triggers); return result; |