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riscv-isa-sim.git
confprec
cs250
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debug_rom
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device_flags
dtm_reset_error
dts_parsing
dynamic
eos18-bringup
factor-out-macros
fix-bf16
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fp-encoding
heterogeneous_mc
hwachav4
increase-stack-size
itrigger-etrigger-cleanup
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master
mmio-hack
mvp
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nolibfdt
p-ext-0.5.2
plctlab-plct-zce-fix2
plic-clint-endian
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decode.h
Age
Commit message (
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Author
Files
Lines
2016-05-23
Gutting direct-access gdb.
Tim Newsome
1
-0
/
+4
2016-05-23
Add writing to DCSR, DPC, DSCRATCH.
Tim Newsome
1
-0
/
+5
2016-05-21
Some bugfixes for CSR reading and setting FS for fflags updates (#43)
Andy Wright
1
-1
/
+4
2016-03-02
Fix ERET serialization strategy
Andrew Waterman
1
-3
/
+6
2016-03-02
Serialize simulator on ERET
Andrew Waterman
1
-0
/
+6
2016-03-02
WIP on priv spec v1.9
Andrew Waterman
1
-3
/
+2
2016-03-01
Upgrade to latest SoftFloat
Andrew Waterman
1
-0
/
+4
2015-11-12
Generate device tree for target machine
Andrew Waterman
1
-0
/
+1
2015-11-12
Access FP regs through a macro
Andrew Waterman
1
-5
/
+6
2015-10-05
more work towards RVC 1.8
Andrew Waterman
1
-4
/
+3
2015-10-02
work towards rvc 1.8
Andrew Waterman
1
-0
/
+3
2015-09-08
Improve instruction fetch
Andrew Waterman
1
-0
/
+2
2015-09-04
Move towards RVC v1.8
Andrew Waterman
1
-22
/
+19
2015-05-31
Add rest of RV32C instructions
Andrew Waterman
1
-0
/
+1
2015-05-31
New RV64C proposal
Andrew Waterman
1
-24
/
+35
2015-04-03
Support setting ISA/subsets with --isa flag
Andrew Waterman
1
-14
/
+3
2015-04-02
Simplify RV32 comparisons
Andrew Waterman
1
-1
/
+0
2015-03-31
Allow writing mstatus.fs even if FPU isn't present
Andrew Waterman
1
-1
/
+5
2015-03-30
Implement RVC draft
Andrew Waterman
1
-6
/
+38
2015-03-26
Serialize counters without throwing C++ exceptions
Andrew Waterman
1
-0
/
+4
2015-03-20
For misaligned fetch, set mepc = addr of branch/jump
Andrew Waterman
1
-1
/
+5
2015-03-12
Update to new privileged spec
Andrew Waterman
1
-26
/
+22
2015-02-08
Use xlen, not xprlen, to refer to x-register width
Andrew Waterman
1
-5
/
+5
2015-01-26
Fix commit log
Andrew Waterman
1
-6
/
+7
2015-01-02
On misaligned fetch, set EPC to target, not branch itself
Andrew Waterman
1
-5
/
+1
2014-12-04
Support 2/4/6/8-byte instructions
Andrew Waterman
1
-19
/
+21
2014-12-04
Set badvaddr on instruction page faults
Andrew Waterman
1
-1
/
+1
2014-11-30
Implement timer faithfully
Andrew Waterman
1
-2
/
+0
2014-09-27
Avoid use of __int128_t
Andrew Waterman
1
-5
/
+1
2014-07-08
Disallow access to FCSR when FP is disabled
Andrew Waterman
1
-17
/
+18
2014-06-13
Commit log now prints while interrupts are enabled.
Christopher Celio
1
-6
/
+2
2014-06-13
Only print commit log if instruction commits
Andrew Waterman
1
-2
/
+2
2014-01-24
Handle CSR permissions correctly
Andrew Waterman
1
-5
/
+6
2014-01-13
Improve performance for branchy code
Andrew Waterman
1
-3
/
+6
2013-12-17
Speed things up quite a bit
Andrew Waterman
1
-11
/
+11
2013-12-09
New RDCYCLE encoding
Andrew Waterman
1
-2
/
+3
2013-11-25
Update to new privileged ISA
Andrew Waterman
1
-6
/
+9
2013-11-05
correctly trap when SR_EA is disabled
Yunsup Lee
1
-0
/
+1
2013-09-27
Added commit logging (--enable-commitlog). Also fixed disasm bug.
Christopher Celio
1
-0
/
+27
2013-09-27
Use WRITE_RD/WRITE_FRD macros to write registers
Andrew Waterman
1
-22
/
+4
2013-09-21
Update ISA encoding and AUIPC semantics
Andrew Waterman
1
-11
/
+15
2013-09-11
Implement zany immediates
Andrew Waterman
1
-91
/
+30
2013-09-10
Add rd field to JAL; drop J
Andrew Waterman
1
-11
/
+2
2013-08-11
Instructions are no longer member functions
Andrew Waterman
1
-17
/
+18
2013-08-08
Disentangle some header files
Andrew Waterman
1
-0
/
+1
2013-07-26
Remove more vector stuff
Andrew Waterman
1
-60
/
+3
2013-07-26
Rip out RVC for now
Andrew Waterman
1
-27
/
+11
2013-07-26
Generate instruction decoder dynamically
Andrew Waterman
1
-1
/
+1
2013-04-24
fixes to correctly simulate the vector unit
Yunsup Lee
1
-0
/
+2
2013-03-25
add BSD license
Andrew Waterman
1
-0
/
+2
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