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cpu.c
Age
Commit message (
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Author
Files
Lines
2022-01-21
target/riscv: Use gdb xml according to max mxlen
LIU Zhiwei
1
-5
/
+3
2022-01-21
target/riscv: Extend pc for runtime pc write
LIU Zhiwei
1
-3
/
+19
2022-01-21
target/riscv: Create xl field in env
LIU Zhiwei
1
-0
/
+1
2022-01-21
target/riscv: rvv-1.0: Allow Zve32f extension to be turned on
Frank Chang
1
-0
/
+1
2022-01-21
target/riscv: rvv-1.0: Add Zve32f extension into RISC-V
Frank Chang
1
-2
/
+2
2022-01-21
target/riscv: rvv-1.0: Allow Zve64f extension to be turned on
Frank Chang
1
-0
/
+1
2022-01-21
target/riscv: rvv-1.0: Add Zve64f extension into RISC-V
Frank Chang
1
-0
/
+4
2022-01-21
target/riscv: Add host cpu type
Yifei Jiang
1
-0
/
+15
2022-01-21
target/riscv: Support setting external interrupt by KVM
Yifei Jiang
1
-1
/
+5
2022-01-21
target/riscv: Support start kernel directly by KVM
Yifei Jiang
1
-0
/
+8
2022-01-08
target/riscv: setup everything for rv64 to support rv128 execution
Frédéric Pétrot
1
-0
/
+20
2022-01-08
target/riscv: array for the 64 upper bits of 128-bit registers
Frédéric Pétrot
1
-0
/
+9
2022-01-08
target/riscv: Fix position of 'experimental' comment
Philipp Tomsich
1
-1
/
+2
2022-01-08
target/riscv: Enable the Hypervisor extension by default
Alistair Francis
1
-1
/
+1
2022-01-08
target/riscv: Mark the Hypervisor extension as non experimental
Alistair Francis
1
-1
/
+1
2021-12-20
target/riscv: Enable bitmanip Zb[abcs] instructions
Vineet Gupta
1
-4
/
+4
2021-12-20
target/riscv: gdb: support vector registers for rv64 & rv32
Hsiangkai Wang
1
-0
/
+2
2021-12-20
target/riscv: drop vector 0.7.1 and add 1.0 support
Frank Chang
1
-8
/
+8
2021-12-20
target/riscv: zfh: add Zfhmin cpu property
Frank Chang
1
-0
/
+1
2021-12-20
target/riscv: zfh: add Zfh cpu property
Frank Chang
1
-0
/
+1
2021-11-02
target/riscv: Make riscv_cpu_tlb_fill sysemu only
Richard Henderson
1
-1
/
+1
2021-10-28
target/riscv: Allow experimental J-ext to be turned on
Alexey Baturo
1
-0
/
+4
2021-10-28
target/riscv: Print new PM CSRs in QEMU logs
Alexey Baturo
1
-0
/
+7
2021-10-28
target/riscv: Support CSRs required for RISC-V PM extension except for the h-...
Alexey Baturo
1
-0
/
+2
2021-10-22
target/riscv: Use riscv_csrrw_debug for cpu_dump
Richard Henderson
1
-44
/
+45
2021-10-22
target/riscv: Add MXL/SXL/UXL to TB_FLAGS
Richard Henderson
1
-0
/
+8
2021-10-22
target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl
Richard Henderson
1
-10
/
+14
2021-10-22
target/riscv: Split misa.mxl and misa.ext
Richard Henderson
1
-33
/
+45
2021-10-22
target/riscv: Organise the CPU properties
Alistair Francis
1
-7
/
+10
2021-10-22
target/riscv: line up all of the registers in the info register dump
Travis Geiselbrecht
1
-5
/
+5
2021-10-07
target/riscv: Remove RVB (replaced by Zb[abcs])
Philipp Tomsich
1
-26
/
+0
2021-10-07
target/riscv: Add x-zba, x-zbb, x-zbc and x-zbs properties
Philipp Tomsich
1
-0
/
+4
2021-09-21
target/riscv: Expose interrupt pending bits as GPIO lines
Alistair Francis
1
-0
/
+30
2021-09-21
target/riscv: Update the ePMP CSR address
Alistair Francis
1
-0
/
+1
2021-09-14
target/riscv: Restrict cpu_exec_interrupt() handler to sysemu
Philippe Mathieu-Daudé
1
-1
/
+1
2021-09-01
target/riscv: Don't wrongly override isa version
LIU Zhiwei
1
-6
/
+8
2021-06-08
target/riscv: rvb: add b-ext version cpu option
Frank Chang
1
-0
/
+23
2021-06-08
target/riscv: rvb: support and turn on B-extension from command line
Kito Cheng
1
-0
/
+4
2021-06-08
target/riscv: Dump CSR mscratch/sscratch/satp
Changbin Du
1
-2
/
+5
2021-06-08
target/riscv: Remove unnecessary riscv_*_names[] declaration
Bin Meng
1
-2
/
+2
2021-05-26
hw/core: Constify TCGCPUOps
Richard Henderson
1
-1
/
+1
2021-05-26
cpu: Move CPUClass::get_phys_page_debug to SysemuCPUOps
Philippe Mathieu-Daudé
1
-1
/
+1
2021-05-26
cpu: Move CPUClass::write_elf* to SysemuCPUOps
Philippe Mathieu-Daudé
1
-2
/
+2
2021-05-26
cpu: Move CPUClass::vmsd to SysemuCPUOps
Philippe Mathieu-Daudé
1
-1
/
+1
2021-05-26
cpu: Introduce SysemuCPUOps structure
Philippe Mathieu-Daudé
1
-0
/
+8
2021-05-26
cpu: Rename CPUClass vmsd -> legacy_vmsd
Philippe Mathieu-Daudé
1
-2
/
+1
2021-05-11
target/riscv: Remove the hardcoded RVXLEN macro
Alistair Francis
1
-1
/
+5
2021-05-11
target/riscv: fix a typo with interrupt names
Emmanuel Blot
1
-1
/
+1
2021-05-11
target/riscv: Add ePMP support for the Ibex CPU
Alistair Francis
1
-0
/
+1
2021-05-11
target/riscv: Add a config option for ePMP
Hou Weiying
1
-0
/
+10
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