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2022-12-20[Support] Move TargetParsers to new componentArchibald Elliott1-742/+0
This is a fairly large changeset, but it can be broken into a few pieces: - `llvm/Support/*TargetParser*` are all moved from the LLVM Support component into a new LLVM Component called "TargetParser". This potentially enables using tablegen to maintain this information, as is shown in https://reviews.llvm.org/D137517. This cannot currently be done, as llvm-tblgen relies on LLVM's Support component. - This also moves two files from Support which use and depend on information in the TargetParser: - `llvm/Support/Host.{h,cpp}` which contains functions for inspecting the current Host machine for info about it, primarily to support getting the host triple, but also for `-mcpu=native` support in e.g. Clang. This is fairly tightly intertwined with the information in `X86TargetParser.h`, so keeping them in the same component makes sense. - `llvm/ADT/Triple.h` and `llvm/Support/Triple.cpp`, which contains the target triple parser and representation. This is very intertwined with the Arm target parser, because the arm architecture version appears in canonical triples on arm platforms. - I moved the relevant unittests to their own directory. And so, we end up with a single component that has all the information about the following, which to me seems like a unified component: - Triples that LLVM Knows about - Architecture names and CPUs that LLVM knows about - CPU detection logic for LLVM Given this, I have also moved `RISCVISAInfo.h` into this component, as it seems to me to be part of that same set of functionality. If you get link errors in your components after this patch, you likely need to add TargetParser into LLVM_LINK_COMPONENTS in CMake. Differential Revision: https://reviews.llvm.org/D137838
2022-12-17[X86] AMD Zen 4 Initial enablementGanesh Gopalasubramanian1-0/+7
Reviewed By: RKSimon Differential Revision: https://reviews.llvm.org/D139073
2022-11-09[X86] Support -march=sierraforest, grandridge, graniterapids.Freddy Ye1-0/+13
Reviewed By: skan, pengfei, MaskRay Differential Revision: https://reviews.llvm.org/D137153
2022-11-04[X86] Support -march=raptorlake, meteorlakeFreddy Ye1-0/+4
Reviewed By: pengfei, skan, MaskRay Differential Revision: https://reviews.llvm.org/D135937
2022-10-31[X86] Add AVX-NE-CONVERT instructions.Freddy Ye1-1/+2
For more details about these instructions, please refer to the latest ISE document: https://www.intel.com/content/www/us/en/develop/download/intel-architecture-instruction-set-extensions-programming-reference.html Reviewed By: pengfei Differential Revision: https://reviews.llvm.org/D135930
2022-10-28[X86] Add AVX-VNNI-INT8 instructions.Freddy Ye1-0/+1
For more details about these instructions, please refer to the latest ISE document: https://www.intel.com/content/www/us/en/develop/download/intel-architecture-instruction-set-extensions-programming-reference.html Reviewed By: pengfei, skan Differential Revision: https://reviews.llvm.org/D135938
2022-10-28[X86] Add AVX-IFMA instructions.Freddy Ye1-0/+1
For more details about these instructions, please refer to the latest ISE document: https://www.intel.com/content/www/us/en/develop/download/intel-architecture-instruction-set-extensions-programming-reference.html Reviewed By: pengfei, skan Differential Revision: https://reviews.llvm.org/D135932
2022-10-27[X86][1/2] SUPPORT RAO-INTPhoebe Wang1-0/+1
For more details about these instructions, please refer to the latest ISE document: https://www.intel.com/content/www/us/en/develop/download/intel-architecture-instruction-set-extensions-programming-reference.html Initial authored by Liu Chen (@LiuChen3) Reviewed By: RKSimon Differential Revision: https://reviews.llvm.org/D135951
2022-10-25[X86] Add CMPCCXADD instructions.Freddy Ye1-0/+1
For more details about these instructions, please refer to the latest ISE document: https://www.intel.com/content/www/us/en/develop/download/intel-architecture-instruction-set-extensions-programming-reference.html Reviewed By: pengfei, skan Differential Revision: https://reviews.llvm.org/D135933
2022-10-22[X86] Add AMX-FP16 instructions.Xiang1 Zhang1-0/+1
Differential Revision: https://reviews.llvm.org/D135941
2022-10-20[X86] Remove redundant static from constexpr. NFCPhoebe Wang1-2/+2
2022-10-20[X86][1/2] Support PREFETCHI instructionsPhoebe Wang1-0/+1
For more details about these instructions, please refer to the latest ISE document: https://www.intel.com/content/www/us/en/develop/download/intel-architecture-instruction-set-extensions-programming-reference.html Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D136040
2022-10-08[X86] Remove AVX512VP2INTERSECT from Sapphire Rapids.Freddy Ye1-5/+5
For more details, please refer to the latest ISE document: https://www.intel.com/content/www/us/en/develop/download/intel-architecture-instruction-set-extensions-programming-reference.html Reviewed By: pengfei Differential Revision: https://reviews.llvm.org/D135509
2022-09-08[llvm] Use std::size instead of llvm::array_lengthofJoe Loser1-7/+7
LLVM contains a helpful function for getting the size of a C-style array: `llvm::array_lengthof`. This is useful prior to C++17, but not as helpful for C++17 or later: `std::size` already has support for C-style arrays. Change call sites to use `std::size` instead. Differential Revision: https://reviews.llvm.org/D133429
2022-09-02[X86] Add missing key feature for core2Freddy Ye1-1/+1
Reviewed By: erichkeane Differential Revision: https://reviews.llvm.org/D133094
2022-07-06[X86] Add RDPRU instructionPaul Robinson1-2/+4
Add support for the RDPRU instruction on Zen2 processors. User-facing features: - Clang option -m[no-]rdpru to enable/disable the feature - Support is implicit for znver2/znver3 processors - Preprocessor symbol __RDPRU__ to indicate support - Header rdpruintrin.h to define intrinsics - "rdpru" mnemonic supported for assembler code Internal features: - Clang builtin __builtin_ia32_rdpru - IR intrinsic @llvm.x86.rdpru Differential Revision: https://reviews.llvm.org/D128934
2022-01-26Revert "Rename llvm::array_lengthof into llvm::size to match std::size from ↵Benjamin Kramer1-7/+7
C++17" This reverts commit ef8206320769ad31422a803a0d6de6077fd231d2. - It conflicts with the existing llvm::size in STLExtras, which will now never be called. - Calling it without llvm:: breaks C++17 compat
2022-01-26Rename llvm::array_lengthof into llvm::size to match std::size from C++17serge-sans-paille1-7/+7
As a conquence move llvm::array_lengthof from STLExtras.h to STLForwardCompat.h (which is included by STLExtras.h so no build breakage expected).
2022-01-21[llvm] Cleanup header dependencies in ADT and Supportserge-sans-paille1-1/+0
The cleanup was manual, but assisted by "include-what-you-use". It consists in 1. Removing unused forward declaration. No impact expected. 2. Removing unused headers in .cpp files. No impact expected. 3. Removing unused headers in .h files. This removes implicit dependencies and is generally considered a good thing, but this may break downstream builds. I've updated llvm, clang, lld, lldb and mlir deps, and included a list of the modification in the second part of the commit. 4. Replacing header inclusion by forward declaration. This has the same impact as 3. Notable changes: - llvm/Support/TargetParser.h no longer includes llvm/Support/AArch64TargetParser.h nor llvm/Support/ARMTargetParser.h - llvm/Support/TypeSize.h no longer includes llvm/Support/WithColor.h - llvm/Support/YAMLTraits.h no longer includes llvm/Support/Regex.h - llvm/ADT/SmallVector.h no longer includes llvm/Support/MemAlloc.h nor llvm/Support/ErrorHandling.h You may need to add some of these headers in your compilation units, if needs be. As an hint to the impact of the cleanup, running clang++ -E -Iinclude -I../llvm/include ../llvm/lib/Support/*.cpp -std=c++14 -fno-rtti -fno-exceptions | wc -l before: 8000919 lines after: 7917500 lines Reduced dependencies also helps incremental rebuilds and is more ccache friendly, something not shown by the above metric :-) Discourse thread on the topic: https://llvm.discourse.group/t/include-what-you-use-include-cleanup/5831
2021-09-06[X86] Add CRC32 feature.Tianqing Wang1-12/+14
d8faf03807ac implemented general-regs-only for X86 by disabling all features with vector instructions. But the CRC32 instruction in SSE4.2 ISA, which uses only GPRs, also becomes unavailable. This patch adds a CRC32 feature for this instruction and allows it to be used with general-regs-only. Reviewed By: pengfei Differential Revision: https://reviews.llvm.org/D105462
2021-08-30[NFC][clang] Move IR-independent parts of target MV support to ↵Andrei Elovikov1-0/+44
X86TargetParser.cpp ...that is located under llvm/lib/Support/. Reviewed By: erichkeane Differential Revision: https://reviews.llvm.org/D108423
2021-08-10[X86] AVX512FP16 instructions enabling 1/6Wang, Pengfei1-5/+7
1. Enable FP16 type support and basic declarations used by following patches. 2. Enable new instructions VMOVW and VMOVSH. Ref.: https://software.intel.com/content/www/us/en/develop/download/intel-avx512-fp16-architecture-specification.html Reviewed By: LuoYuanke Differential Revision: https://reviews.llvm.org/D105263
2021-04-13[X86] Support -march=rocketlakeFreddy Ye1-0/+3
Reviewed By: skan, craig.topper, MaskRay Differential Revision: https://reviews.llvm.org/D100085
2021-04-12[X86] Remove FeatureCLWB from FeaturesICLClientFreddy Ye1-4/+4
Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D100279
2021-03-08[X86] Refine "Support -march=alderlake"Freddy Ye1-3/+6
Refine "Support -march=alderlake" Compare with tremont, it includes 25 more new features. They are adx, aes, avx, avx2, avxvnni, bmi, bmi2, cldemote, f16c, fma, hreset, invpcid, kl, lzcnt, movdir64b, movdiri, pclmulqdq, pconfig, pku, serialize, shstk, vaes, vpclmulqdq, waitpkg, widekl. Reviewed By: pengfei Differential Revision: https://reviews.llvm.org/D97832
2021-01-21[llvm] Don't include StringSwitch.h where unnecessary (NFC)Kazu Hirata1-1/+0
2020-10-31[X86] Support Intel avxvnniLiu, Chen31-2/+5
This patch mainly made the following changes: 1. Support AVX-VNNI instructions; 2. Introduce ExplicitVEXPrefix flag so that vpdpbusd/vpdpbusds/vpdpbusds/vpdpbusds instructions only use vex-encoding when user explicity add {vex} prefix. Differential Revision: https://reviews.llvm.org/D89105
2020-10-24[X86] Add a stub for Intel's alderlake.Benjamin Kramer1-0/+5
No scheduling, no autodetection.
2020-10-24[X86] Add a stub for znver3 based on the little public information there is ↵Benjamin Kramer1-0/+4
in AMD's manuals No scheduling, no autodetection. Just enough so -march=znver3 works.
2020-10-22[X86] Add User Interrupts(UINTR) instructionsTianqing Wang1-1/+3
For more details about these instructions, please refer to the latest ISE document: https://software.intel.com/en-us/download/intel-architecture-instruction-set-extensions-programming-reference. Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D89301
2020-10-13[X86] Add HRESET instruction.Wang, Pengfei1-0/+1
For more details about these instructions, please refer to the latest ISE document: https://software.intel.com/en-us/download/intel-architecture-instruction-set-extensions-programming-reference. Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D89102
2020-10-12[X86] Support -march=x86-64-v[234]Fangrui Song1-0/+28
PR47686. These micro-architecture levels are defined in the x86-64 psABI: https://gitlab.com/x86-psABIs/x86-64-ABI/-/commit/77566eb03bc6a326811cb7e9 GCC 11 will support these levels. Note, -mtune=x86-64-v[234] are invalid and __builtin_cpu_is cannot be used on them. Reviewed By: craig.topper, RKSimon Differential Revision: https://reviews.llvm.org/D89197
2020-10-10[X86] Delete redundant 'static' from namespace scope 'static constexpr'. NFCFangrui Song1-156/+149
This decreases 7 lines as the result of packing more bits on one line.
2020-09-30[X86] Support Intel Key LockerXiang1 Zhang1-1/+5
Key Locker provides a mechanism to encrypt and decrypt data with an AES key without having access to the raw key value by converting AES keys into “handles”. These handles can be used to perform the same encryption and decryption operations as the original AES keys, but they only work on the current system and only until they are revoked. If software revokes Key Locker handles (e.g., on a reboot), then any previous handles can no longer be used. Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D88398
2020-09-08[X86] SSE4_A should only imply SSE3 not SSSE3 in the frontend.Craig Topper1-1/+1
SSE4_1 and SSE4_2 due imply SSSE3. So I guess I got confused when switching the code to being table based in D83273. Fixes PR47464
2020-08-25[X86] Support -march=sapphirerapidsFreddy Ye1-0/+7
Support -march=sapphirerapids for x86. Compare with Icelake Server, it includes 14 more new features. They are amxtile, amxint8, amxbf16, avx512bf16, avx512vp2intersect, cldemote, enqcmd, movdir64b, movdiri, ptwrite, serialize, shstk, tsxldtrk, waitpkg. Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D86503
2020-08-06[X86] Rename X86::getImpliedFeatures to X86::updateImpliedFeatures and pass ↵Craig Topper1-13/+9
clang's StringMap directly to it. No point in building a vector of StringRefs for clang to apply to the StringMap. Just pass the StringMap and modify it directly.
2020-08-04[X86] Optimize getImpliedDisabledFeatures & getImpliedEnabledFeatures after ↵Fangrui Song1-10/+29
D83273 Previously the time complexity is O(|number of paths from the root to an implied feature| * CPU_FWATURE_MAX) where CPU_FEATURE_MAX is 92. The number of paths can be large (theoretically exponential). For an inline asm statement, there is a code path `clang::Parser::ParseAsmStatement -> clang::Sema::ActOnGCCAsmStmt -> ASTContext::getFunctionFeatureMap` leading to potentially many calls of getImpliedEnabledFeatures (41 for my -march=native case). We should improve the performance a bit in case the number of inline asm statements is large (Linux kernel builds). Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D85257
2020-07-09Recommit "[X86] Merge the FEATURE_64BIT and FEATURE_EM64T bits in ↵Craig Topper1-10/+28
X86TargetParser.def." This time without the change to make operator| use operator&=. That seems to be the source of the gcc 5.3 miscompile. Original commit message: These represent the same thing but 64BIT only showed up from getHostCPUFeatures providing a list of featuers to clang. While EM64T showed up from getting the features for a named CPU. EM64T didn't have a string specifically so it would not be passed up to clang when getting features for a named CPU. While 64bit needed a name since that's how it is index. Merge them by filtering 64bit out before sending features to clang for named CPUs.
2020-07-09Revert 51b0da73 "Recommit "[X86] Merge the FEATURE_64BIT and FEATURE_EM64T ↵Hans Wennborg1-27/+16
bits in X86TargetParser.def."" It gets miscompiled with GCC 5.3, causing Clang to crash with "error: unknown target CPU 'x86-64'" See the llvm-commits thread for reproduction steps. This reverts commit 51b0da731af75c68dd521e04cc576d5a611b1612.
2020-07-07Revert "[X86] Add back the assert in getImpliedFeatures that I removed in ↵Nico Weber1-2/+0
ef4cc70f3ed2a91e0a48c6448c517c3ba34c2846" This reverts commit 91f70675cc6e5c872e0059c11d797b8726eeac67. It seems to break most (all?) hwasan tests.
2020-07-07Recommit "[X86] Merge the FEATURE_64BIT and FEATURE_EM64T bits in ↵Craig Topper1-16/+27
X86TargetParser.def." These represent the same thing but 64BIT only showed up from getHostCPUFeatures providing a list of featuers to clang. While EM64T showed up from getting the features for a named CPU. EM64T didn't have a string specifically so it would not be passed up to clang when getting features for a named CPU. While 64bit needed a name since that's how it is index. Merge them by filtering 64bit out before sending features to clang for named CPUs.
2020-07-07Revert "[X86] Merge the FEATURE_64BIT and FEATURE_EM64T bits in ↵Craig Topper1-27/+16
X86TargetParser.def." An accidental change snuck in here This reverts commit f1d290d81298092b693076725cef4f34e951e974.
2020-07-07[X86] Merge the FEATURE_64BIT and FEATURE_EM64T bits in X86TargetParser.def.Craig Topper1-16/+27
These represent the same thing but 64BIT only showed up from getHostCPUFeatures providing a list of featuers to clang. While EM64T showed up from getting the features for a named CPU. EM64T didn't have a string specifically so it would not be passed up to clang when getting features for a named CPU. While 64bit needed a name since that's how it is index. Merge them by filtering 64bit out before sending features to clang for named CPUs.
2020-07-07[X86] Add back the assert in getImpliedFeatures that I removed in ↵Craig Topper1-0/+2
ef4cc70f3ed2a91e0a48c6448c517c3ba34c2846 I've added additional features to the table so I want to see if the bots are happier with this.
2020-07-07[X86] Add 64bit and retpoline-external-thunk to list of featuers in ↵Craig Topper1-0/+4
X86TargetParser.def. '64bit' shows up from -march=native on 64-bit capable CPUs. 'retpoline-eternal-thunk' isn't a real feature but shows up when -mretpoline-external-thunk is passed to clang.
2020-07-07[X86] Remove assert for missing features from X86::getImpliedFeaturesCraig Topper1-2/+0
This is failing on the bots. Remove while I try to figure out what feature I missed in the table.
2020-07-06[X86] Move the feature dependency handling in ↵Craig Topper1-6/+187
X86TargetInfo::setFeatureEnabledImpl to a table based lookup in X86TargetParser.cpp Previously we had to specify the forward and backwards feature dependencies separately which was error prone. And as dependencies have gotten more complex it was hard to be sure the transitive dependencies were handled correctly. The way it was written was also not super readable. This patch replaces everything with a table that lists what features a feature is dependent on directly. Then we can recursively walk through the table to find the transitive dependencies. This is largely based on how we handle subtarget features in the MC layer from the tablegen descriptions. Differential Revision: https://reviews.llvm.org/D83273
2020-07-06[X86] Remove duplicate SSE4A feature bit from X86TargetParser.def. NFCCraig Topper1-4/+4
We had both SSE4A and SSE4_A. So remove one of them.
2020-06-30Fixup BDVER1 and ZNVER1 definitions that were accidentally changed in recent ↵Douglas Yung1-11/+10
refactor. - BDVER1 - Duplicate FeatureLZCNT removed - ZNVER1 - Duplicate FeatureLZCNT removed - Removed unsupported FeatureLWP - Swapped FeatureMMX and FeatureMOVBE to be in alphabetical order
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