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author | Craig Topper <craig.topper@intel.com> | 2020-07-07 19:01:22 -0700 |
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committer | Craig Topper <craig.topper@intel.com> | 2020-07-07 19:01:58 -0700 |
commit | 51b0da731af75c68dd521e04cc576d5a611b1612 (patch) | |
tree | 373fce168154d3f084624b83956b3261a4d5ef53 /llvm/lib/Support/X86TargetParser.cpp | |
parent | 1e9d0811c9bf40abbe07d591057869568f140036 (diff) | |
download | llvm-51b0da731af75c68dd521e04cc576d5a611b1612.zip llvm-51b0da731af75c68dd521e04cc576d5a611b1612.tar.gz llvm-51b0da731af75c68dd521e04cc576d5a611b1612.tar.bz2 |
Recommit "[X86] Merge the FEATURE_64BIT and FEATURE_EM64T bits in X86TargetParser.def."
These represent the same thing but 64BIT only showed up from
getHostCPUFeatures providing a list of featuers to clang. While
EM64T showed up from getting the features for a named CPU.
EM64T didn't have a string specifically so it would not be passed
up to clang when getting features for a named CPU. While 64bit
needed a name since that's how it is index.
Merge them by filtering 64bit out before sending features to clang
for named CPUs.
Diffstat (limited to 'llvm/lib/Support/X86TargetParser.cpp')
-rw-r--r-- | llvm/lib/Support/X86TargetParser.cpp | 43 |
1 files changed, 27 insertions, 16 deletions
diff --git a/llvm/lib/Support/X86TargetParser.cpp b/llvm/lib/Support/X86TargetParser.cpp index df03f63..cbb7f61 100644 --- a/llvm/lib/Support/X86TargetParser.cpp +++ b/llvm/lib/Support/X86TargetParser.cpp @@ -48,6 +48,14 @@ public: return (Bits[I / 32] & Mask) != 0; } + constexpr FeatureBitset &operator&=(const FeatureBitset &RHS) { + for (unsigned I = 0, E = array_lengthof(Bits); I != E; ++I) { + uint32_t NewBits = Bits[I] & RHS.Bits[I]; + Bits[I] = NewBits; + } + return *this; + } + constexpr FeatureBitset &operator|=(const FeatureBitset &RHS) { for (unsigned I = 0, E = array_lengthof(Bits); I != E; ++I) { uint32_t NewBits = Bits[I] | RHS.Bits[I]; @@ -57,16 +65,14 @@ public: } constexpr FeatureBitset operator&(const FeatureBitset &RHS) const { - FeatureBitset Result; - for (unsigned I = 0, E = array_lengthof(Bits); I != E; ++I) - Result.Bits[I] = Bits[I] & RHS.Bits[I]; + FeatureBitset Result = *this; + Result &= RHS; return Result; } constexpr FeatureBitset operator|(const FeatureBitset &RHS) const { - FeatureBitset Result; - for (unsigned I = 0, E = array_lengthof(Bits); I != E; ++I) - Result.Bits[I] = Bits[I] | RHS.Bits[I]; + FeatureBitset Result = *this; + Result |= RHS; return Result; } @@ -111,10 +117,10 @@ static constexpr FeatureBitset FeaturesPentium4 = static constexpr FeatureBitset FeaturesPrescott = FeaturesPentium4 | FeatureSSE3; static constexpr FeatureBitset FeaturesNocona = - FeaturesPrescott | FeatureEM64T | FeatureCMPXCHG16B; + FeaturesPrescott | Feature64BIT | FeatureCMPXCHG16B; // Basic 64-bit capable CPU. -static constexpr FeatureBitset FeaturesX86_64 = FeaturesPentium4 | FeatureEM64T; +static constexpr FeatureBitset FeaturesX86_64 = FeaturesPentium4 | Feature64BIT; // Intel Core CPUs static constexpr FeatureBitset FeaturesCore2 = @@ -201,7 +207,7 @@ static constexpr FeatureBitset FeaturesAthlon = static constexpr FeatureBitset FeaturesAthlonXP = FeaturesAthlon | FeatureFXSR | FeatureSSE; static constexpr FeatureBitset FeaturesK8 = - FeaturesAthlonXP | FeatureSSE2 | FeatureEM64T; + FeaturesAthlonXP | FeatureSSE2 | Feature64BIT; static constexpr FeatureBitset FeaturesK8SSE3 = FeaturesK8 | FeatureSSE3; static constexpr FeatureBitset FeaturesAMDFAM10 = FeaturesK8SSE3 | FeatureCMPXCHG16B | FeatureLZCNT | FeaturePOPCNT | @@ -209,7 +215,7 @@ static constexpr FeatureBitset FeaturesAMDFAM10 = // Bobcat architecture processors. static constexpr FeatureBitset FeaturesBTVER1 = - FeatureX87 | FeatureCMPXCHG8B | FeatureCMPXCHG16B | FeatureEM64T | + FeatureX87 | FeatureCMPXCHG8B | FeatureCMPXCHG16B | Feature64BIT | FeatureFXSR | FeatureLZCNT | FeatureMMX | FeaturePOPCNT | FeaturePRFCHW | FeatureSSE | FeatureSSE2 | FeatureSSE3 | FeatureSSSE3 | FeatureSSE4_A | FeatureSAHF; @@ -220,7 +226,7 @@ static constexpr FeatureBitset FeaturesBTVER2 = // AMD Bulldozer architecture processors. static constexpr FeatureBitset FeaturesBDVER1 = FeatureX87 | FeatureAES | FeatureAVX | FeatureCMPXCHG8B | - FeatureCMPXCHG16B | FeatureEM64T | FeatureFMA4 | FeatureFXSR | FeatureLWP | + FeatureCMPXCHG16B | Feature64BIT | FeatureFMA4 | FeatureFXSR | FeatureLWP | FeatureLZCNT | FeatureMMX | FeaturePCLMUL | FeaturePOPCNT | FeaturePRFCHW | FeatureSAHF | FeatureSSE | FeatureSSE2 | FeatureSSE3 | FeatureSSSE3 | FeatureSSE4_1 | FeatureSSE4_2 | FeatureSSE4_A | FeatureXOP | FeatureXSAVE; @@ -236,7 +242,7 @@ static constexpr FeatureBitset FeaturesBDVER4 = static constexpr FeatureBitset FeaturesZNVER1 = FeatureX87 | FeatureADX | FeatureAES | FeatureAVX | FeatureAVX2 | FeatureBMI | FeatureBMI2 | FeatureCLFLUSHOPT | FeatureCLZERO | - FeatureCMPXCHG8B | FeatureCMPXCHG16B | FeatureEM64T | FeatureF16C | + FeatureCMPXCHG8B | FeatureCMPXCHG16B | Feature64BIT | FeatureF16C | FeatureFMA | FeatureFSGSBASE | FeatureFXSR | FeatureLZCNT | FeatureMMX | FeatureMOVBE | FeatureMWAITX | FeaturePCLMUL | FeaturePOPCNT | FeaturePRFCHW | FeatureRDRND | FeatureRDSEED | FeatureSAHF | FeatureSHA | @@ -363,7 +369,7 @@ static constexpr ProcInfo Processors[] = { X86::CPUKind llvm::X86::parseArchX86(StringRef CPU, bool Only64Bit) { for (const auto &P : Processors) - if (P.Name == CPU && (P.Features[FEATURE_EM64T] || !Only64Bit)) + if (P.Name == CPU && (P.Features[FEATURE_64BIT] || !Only64Bit)) return P.Kind; return CK_None; @@ -372,7 +378,7 @@ X86::CPUKind llvm::X86::parseArchX86(StringRef CPU, bool Only64Bit) { void llvm::X86::fillValidCPUArchList(SmallVectorImpl<StringRef> &Values, bool Only64Bit) { for (const auto &P : Processors) - if (!P.Name.empty() && (P.Features[FEATURE_EM64T] || !Only64Bit)) + if (!P.Name.empty() && (P.Features[FEATURE_64BIT] || !Only64Bit)) Values.emplace_back(P.Name); } @@ -401,7 +407,6 @@ static constexpr FeatureBitset ImpliedFeaturesCLZERO = {}; static constexpr FeatureBitset ImpliedFeaturesCMOV = {}; static constexpr FeatureBitset ImpliedFeaturesCMPXCHG16B = {}; static constexpr FeatureBitset ImpliedFeaturesCMPXCHG8B = {}; -static constexpr FeatureBitset ImpliedFeaturesEM64T = {}; static constexpr FeatureBitset ImpliedFeaturesENQCMD = {}; static constexpr FeatureBitset ImpliedFeaturesFSGSBASE = {}; static constexpr FeatureBitset ImpliedFeaturesFXSR = {}; @@ -528,8 +533,14 @@ void llvm::X86::getFeaturesForCPU(StringRef CPU, [&](const ProcInfo &P) { return P.Name == CPU; }); assert(I != std::end(Processors) && "Processor not found!"); + FeatureBitset Bits = I->Features; + + // Remove the 64-bit feature which we only use to validate if a CPU can + // be used with 64-bit mode. + Bits &= ~Feature64BIT; + // Add the string version of all set bits. - getFeatureBitsAsStrings(I->Features, EnabledFeatures); + getFeatureBitsAsStrings(Bits, EnabledFeatures); } // For each feature that is (transitively) implied by this feature, set it. |