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authorTianqing Wang <tianqing.wang@intel.com>2020-10-22 16:46:07 +0800
committerWang, Pengfei <pengfei.wang@intel.com>2020-10-22 17:33:07 +0800
commitbe39a6fe6fc6c30186152863a7fac624e22262f7 (patch)
treea70e93299868cd0ca794545408d67529007fa3b9 /llvm/lib/Support/X86TargetParser.cpp
parentefcb3952e0e90a49ed354d04dbde713cc6258ae1 (diff)
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[X86] Add User Interrupts(UINTR) instructions
For more details about these instructions, please refer to the latest ISE document: https://software.intel.com/en-us/download/intel-architecture-instruction-set-extensions-programming-reference. Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D89301
Diffstat (limited to 'llvm/lib/Support/X86TargetParser.cpp')
-rw-r--r--llvm/lib/Support/X86TargetParser.cpp4
1 files changed, 3 insertions, 1 deletions
diff --git a/llvm/lib/Support/X86TargetParser.cpp b/llvm/lib/Support/X86TargetParser.cpp
index 698dc4a..7b1e0c0 100644
--- a/llvm/lib/Support/X86TargetParser.cpp
+++ b/llvm/lib/Support/X86TargetParser.cpp
@@ -204,7 +204,8 @@ constexpr FeatureBitset FeaturesSapphireRapids =
FeaturesICLServer | FeatureAMX_TILE | FeatureAMX_INT8 | FeatureAMX_BF16 |
FeatureAVX512BF16 | FeatureAVX512VP2INTERSECT | FeatureCLDEMOTE |
FeatureENQCMD | FeatureMOVDIR64B | FeatureMOVDIRI | FeaturePTWRITE |
- FeatureSERIALIZE | FeatureSHSTK | FeatureTSXLDTRK | FeatureWAITPKG;
+ FeatureSERIALIZE | FeatureSHSTK | FeatureTSXLDTRK | FeatureUINTR |
+ FeatureWAITPKG;
// Intel Atom processors.
// Bonnell has feature parity with Core2 and adds MOVBE.
@@ -481,6 +482,7 @@ constexpr FeatureBitset ImpliedFeaturesSGX = {};
constexpr FeatureBitset ImpliedFeaturesSHSTK = {};
constexpr FeatureBitset ImpliedFeaturesTBM = {};
constexpr FeatureBitset ImpliedFeaturesTSXLDTRK = {};
+constexpr FeatureBitset ImpliedFeaturesUINTR = {};
constexpr FeatureBitset ImpliedFeaturesWAITPKG = {};
constexpr FeatureBitset ImpliedFeaturesWBNOINVD = {};
constexpr FeatureBitset ImpliedFeaturesVZEROUPPER = {};