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| author | Freddy Ye <freddy.ye@intel.com> | 2022-10-08 14:27:06 +0800 |
|---|---|---|
| committer | Freddy Ye <freddy.ye@intel.com> | 2022-10-08 14:54:03 +0800 |
| commit | 566c277c64f8f76d8911aa5fd931903a357ed7be (patch) | |
| tree | ad1e5d37032aa5de7fe5939a577d3b270fe332d7 /llvm/lib/Support/X86TargetParser.cpp | |
| parent | f4ccb577f8c8136d2b03f7a1e6475877b147b767 (diff) | |
| download | llvm-566c277c64f8f76d8911aa5fd931903a357ed7be.zip llvm-566c277c64f8f76d8911aa5fd931903a357ed7be.tar.gz llvm-566c277c64f8f76d8911aa5fd931903a357ed7be.tar.bz2 | |
[X86] Remove AVX512VP2INTERSECT from Sapphire Rapids.
For more details, please refer to the latest ISE document: https://www.intel.com/content/www/us/en/develop/download/intel-architecture-instruction-set-extensions-programming-reference.html
Reviewed By: pengfei
Differential Revision: https://reviews.llvm.org/D135509
Diffstat (limited to 'llvm/lib/Support/X86TargetParser.cpp')
| -rw-r--r-- | llvm/lib/Support/X86TargetParser.cpp | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/llvm/lib/Support/X86TargetParser.cpp b/llvm/lib/Support/X86TargetParser.cpp index 1f72f58..8c65542 100644 --- a/llvm/lib/Support/X86TargetParser.cpp +++ b/llvm/lib/Support/X86TargetParser.cpp @@ -203,10 +203,10 @@ constexpr FeatureBitset FeaturesTigerlake = FeatureCLWB | FeatureMOVDIRI | FeatureSHSTK | FeatureKL | FeatureWIDEKL; constexpr FeatureBitset FeaturesSapphireRapids = FeaturesICLServer | FeatureAMX_BF16 | FeatureAMX_INT8 | FeatureAMX_TILE | - FeatureAVX512BF16 | FeatureAVX512FP16 | FeatureAVX512VP2INTERSECT | - FeatureAVXVNNI | FeatureCLDEMOTE | FeatureENQCMD | FeatureMOVDIR64B | - FeatureMOVDIRI | FeaturePTWRITE | FeatureSERIALIZE | FeatureSHSTK | - FeatureTSXLDTRK | FeatureUINTR | FeatureWAITPKG; + FeatureAVX512BF16 | FeatureAVX512FP16 | FeatureAVXVNNI | FeatureCLDEMOTE | + FeatureENQCMD | FeatureMOVDIR64B | FeatureMOVDIRI | FeaturePTWRITE | + FeatureSERIALIZE | FeatureSHSTK | FeatureTSXLDTRK | FeatureUINTR | + FeatureWAITPKG; // Intel Atom processors. // Bonnell has feature parity with Core2 and adds MOVBE. @@ -367,7 +367,7 @@ constexpr ProcInfo Processors[] = { // Tigerlake microarchitecture based processors. { {"tigerlake"}, CK_Tigerlake, FEATURE_AVX512VP2INTERSECT, FeaturesTigerlake }, // Sapphire Rapids microarchitecture based processors. - { {"sapphirerapids"}, CK_SapphireRapids, FEATURE_AVX512VP2INTERSECT, FeaturesSapphireRapids }, + { {"sapphirerapids"}, CK_SapphireRapids, FEATURE_AVX512BF16, FeaturesSapphireRapids }, // Alderlake microarchitecture based processors. { {"alderlake"}, CK_Alderlake, FEATURE_AVX2, FeaturesAlderlake }, // Knights Landing processor. |