diff options
| author | Fangrui Song <i@maskray.me> | 2020-10-12 09:35:22 -0700 |
|---|---|---|
| committer | Fangrui Song <i@maskray.me> | 2020-10-12 10:29:46 -0700 |
| commit | 012dd42e027e2ff3d183cc9dcf27004cf9711720 (patch) | |
| tree | 8d69f609bcd2ac39230300ed996be87cef4b3afc /llvm/lib/Support/X86TargetParser.cpp | |
| parent | e944455eaf1ed3b3bfe9876c5478ce18e9975eea (diff) | |
| download | llvm-012dd42e027e2ff3d183cc9dcf27004cf9711720.zip llvm-012dd42e027e2ff3d183cc9dcf27004cf9711720.tar.gz llvm-012dd42e027e2ff3d183cc9dcf27004cf9711720.tar.bz2 | |
[X86] Support -march=x86-64-v[234]
PR47686. These micro-architecture levels are defined in the x86-64 psABI:
https://gitlab.com/x86-psABIs/x86-64-ABI/-/commit/77566eb03bc6a326811cb7e9
GCC 11 will support these levels.
Note, -mtune=x86-64-v[234] are invalid and __builtin_cpu_is cannot be
used on them.
Reviewed By: craig.topper, RKSimon
Differential Revision: https://reviews.llvm.org/D89197
Diffstat (limited to 'llvm/lib/Support/X86TargetParser.cpp')
| -rw-r--r-- | llvm/lib/Support/X86TargetParser.cpp | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/llvm/lib/Support/X86TargetParser.cpp b/llvm/lib/Support/X86TargetParser.cpp index 1e8569b..35582a9 100644 --- a/llvm/lib/Support/X86TargetParser.cpp +++ b/llvm/lib/Support/X86TargetParser.cpp @@ -137,6 +137,15 @@ constexpr FeatureBitset FeaturesNocona = // Basic 64-bit capable CPU. constexpr FeatureBitset FeaturesX86_64 = FeaturesPentium4 | Feature64BIT; +constexpr FeatureBitset FeaturesX86_64_V2 = FeaturesX86_64 | FeatureSAHF | + FeaturePOPCNT | FeatureSSE4_2 | + FeatureCMPXCHG16B; +constexpr FeatureBitset FeaturesX86_64_V3 = + FeaturesX86_64_V2 | FeatureAVX2 | FeatureBMI | FeatureBMI2 | FeatureF16C | + FeatureFMA | FeatureLZCNT | FeatureMOVBE | FeatureXSAVE; +constexpr FeatureBitset FeaturesX86_64_V4 = FeaturesX86_64_V3 | + FeatureAVX512BW | FeatureAVX512CD | + FeatureAVX512DQ | FeatureAVX512VL; // Intel Core CPUs constexpr FeatureBitset FeaturesCore2 = @@ -383,10 +392,15 @@ constexpr ProcInfo Processors[] = { { {"znver2"}, CK_ZNVER2, FEATURE_AVX2, FeaturesZNVER2 }, // Generic 64-bit processor. { {"x86-64"}, CK_x86_64, ~0U, FeaturesX86_64 }, + { {"x86-64-v2"}, CK_x86_64_v2, ~0U, FeaturesX86_64_V2 }, + { {"x86-64-v3"}, CK_x86_64_v3, ~0U, FeaturesX86_64_V3 }, + { {"x86-64-v4"}, CK_x86_64_v4, ~0U, FeaturesX86_64_V4 }, // Geode processors. { {"geode"}, CK_Geode, ~0U, FeaturesGeode }, }; +constexpr const char *NoTuneList[] = {"x86-64-v2", "x86-64-v3", "x86-64-v4"}; + X86::CPUKind llvm::X86::parseArchX86(StringRef CPU, bool Only64Bit) { for (const auto &P : Processors) if (P.Name == CPU && (P.Features[FEATURE_64BIT] || !Only64Bit)) @@ -395,6 +409,12 @@ X86::CPUKind llvm::X86::parseArchX86(StringRef CPU, bool Only64Bit) { return CK_None; } +X86::CPUKind llvm::X86::parseTuneCPU(StringRef CPU, bool Only64Bit) { + if (llvm::is_contained(NoTuneList, CPU)) + return CK_None; + return parseArchX86(CPU, Only64Bit); +} + void llvm::X86::fillValidCPUArchList(SmallVectorImpl<StringRef> &Values, bool Only64Bit) { for (const auto &P : Processors) @@ -402,6 +422,14 @@ void llvm::X86::fillValidCPUArchList(SmallVectorImpl<StringRef> &Values, Values.emplace_back(P.Name); } +void llvm::X86::fillValidTuneCPUList(SmallVectorImpl<StringRef> &Values, + bool Only64Bit) { + for (const ProcInfo &P : Processors) + if (!P.Name.empty() && (P.Features[FEATURE_64BIT] || !Only64Bit) && + !llvm::is_contained(NoTuneList, P.Name)) + Values.emplace_back(P.Name); +} + ProcessorFeatures llvm::X86::getKeyFeature(X86::CPUKind Kind) { // FIXME: Can we avoid a linear search here? The table might be sorted by // CPUKind so we could binary search? |