riscv-gnu-toolchain/gdb.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2013-01-17	include/opcode/	Yufeng Zhang	5	-10/+28
2013-01-16	Add OPERAND_TYPE_IMM32_64	H.J. Lu	4	-2/+16
2013-01-15	* config/tc-v850.c (md_assemble): Allow signed values for	Nick Clifton	3	-2/+10
2013-01-14	* metag-dis.c (REG_WIDTH): Increase to 64.	Nick Clifton	2	-1/+5
2013-01-11	include/opcode/	Peter Bergner	3	-1/+76
2013-01-10	* common.h: Fix case of "Meta".	Nick Clifton	7	-0/+3409
2013-01-07	oops - typo correction.	Nick Clifton	1	-1/+1
2013-01-07	(make_instruction): Rename to cr16_make_instruction.	Nick Clifton	2	-4/+9
2013-01-04	* archures.c: Add support for MIPS r5900	Nick Clifton	3	-138/+341
2013-01-04	opcodes/	Yufeng Zhang	3	-8/+33
2013-01-04	* aarch64-opc.c (aarch64_prfops): Update to support PLIL1KEEP,	Nick Clifton	2	-14/+19
2013-01-02	Update copyright year to 2013	H.J. Lu	2	-2/+6
2013-01-02	opcodes/ChangeLog	Nick Clifton	3	-1111/+1140
2012-12-17	Add copyright notices	Nick Clifton	11	-2/+187
2012-12-13	PR binutils/14950	Alan Modra	2	-65/+46
2012-12-10	Add copyright notices	Nick Clifton	13	-0/+81
2012-11-30	2012-11-30 Oleg Raikhman <oleg@adapteva.com>	Joern Rennecke	4	-121/+126
2012-11-29	opcodes/	Roland McGrath	2	-5/+9
2012-11-29	opcodes/Changelog:	Michael Eager	3	-7/+13
2012-11-23	include/opcode/	Alan Modra	2	-24/+76
2012-11-21	Add swap byte (swapb) and swap halfword (swaph) opcodes.	Michael Eager	3	-2/+9
2012-11-21	Add stack high register and stack low register for MicroBlaze	Michael Eager	3	-0/+15
2012-11-20	Fix opcode for 64-bit jecxz	H.J. Lu	3	-2/+9
2012-11-20	2012-11-20 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>	Andreas Krebbel	2	-2/+6
2012-11-14	opcodes/	Michael Eager	4	-4/+45
2012-11-14	Add clz opcode.	Michael Eager	3	-2/+8
2012-11-14	Add the endian reversing versions of load/store instructions;	Michael Eager	3	-2/+16
2012-11-09	2012-11-09 Nick Clifton <nickc@redhat.com>	Nick Clifton	4	-0/+9
2012-11-09	Remove trailing redundant `;'	H.J. Lu	3	-2/+7
2012-11-08	Regenerate.	Alan Modra	2	-0/+15
2012-11-05	* configure.in: Apply 2012-09-10 change to config.in here.	Alan Modra	2	-2/+7
2012-10-26	2012-10-26 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>	Andreas Krebbel	4	-3/+32
2012-10-26	gas/testsuite:	Christian Groessler	3	-61/+59
2012-10-26	* ppc-opc (powerpc_opcodes): "lfdp" and "stfdp" use DS offset.	Alan Modra	2	-2/+6
2012-10-24	gas/testsuite/	Roland McGrath	2	-58/+66
2012-10-22	opcodes/	Peter Bergner	2	-1/+5
2012-10-18	* tic54x-dis.c (print_instruction): Don't use K&R style.	Tom Tromey	2	-38/+37
2012-10-18	* aarch64-asm.c (aarch64_ins_ldst_reglist): Initialize	Kai Tietz	3	-7/+16
2012-10-15	Updated the system register table.	Yufeng Zhang	2	-4/+8
2012-10-15	Added the changelog for the previous commit.	Yufeng Zhang	1	-0/+6
2012-10-15	Added missing alignment check to load/store uimm12 immediate offset.	Yufeng Zhang	1	-1/+1
2012-10-11	2012-10-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>	Richard Earnshaw	2	-5/+10
2012-10-09	Add AMD bdver3 support.	Nagajyothi Eggone	3	-0/+13
2012-10-05	opcodes/	Peter Bergner	3	-1/+21
2012-10-04	* v850-dis.c (disassemble): Place square parentheses around second	Nick Clifton	2	-4/+21
2012-10-04	2012-10-04 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>	Andreas Krebbel	4	-34/+90
2012-09-28	Don't abort() when disassembling bad moxie instructions.	Anthony Green	3	-29/+102
2012-09-25	Add missing Cpu flags in bd and bt cores	H.J. Lu	3	-16/+23
2012-09-20	Replace CpuSSE3 with CpuCX16 for cmpxchg16b	H.J. Lu	6	-2964/+2989
2012-09-18	2012-09-18 Kyrylo Tkachov <kyrylo.tkachov@arm.com>	Richard Earnshaw	2	-28/+33