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author | Andreas Krebbel <Andreas.Krebbel@de.ibm.com> | 2012-10-26 09:41:55 +0000 |
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committer | Andreas Krebbel <Andreas.Krebbel@de.ibm.com> | 2012-10-26 09:41:55 +0000 |
commit | aac129d77611fab3db3f354c67c0f2c9406fa828 (patch) | |
tree | c4317a43a47fea63861ce6eaac42c7b70be96166 /opcodes | |
parent | 747a4ac1f42fa0fc458b07ca0370c87f9cd7ad44 (diff) | |
download | gdb-aac129d77611fab3db3f354c67c0f2c9406fa828.zip gdb-aac129d77611fab3db3f354c67c0f2c9406fa828.tar.gz gdb-aac129d77611fab3db3f354c67c0f2c9406fa828.tar.bz2 |
2012-10-26 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
* s390-mkopc.c: Accept empty lines in s390-opc.txt.
* s390-opc.c: Add M_20OPT field. New instruction formats RRF_RURR2 and RRF_RMRR.
* s390-opc.txt: Add new instructions. New instruction type for lptea.
2012-10-26 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
* gas/testsuite/gas/s390/zarch-z10.d: Refreshed.
* gas/testsuite/gas/s390/zarch-z10.s: Refreshed.
* gas/testsuite/gas/s390/zarch-z196.d: Refreshed.
* gas/testsuite/gas/s390/zarch-z196.s: Refreshed.
* gas/testsuite/gas/s390/zarch-z9-109.d: Refreshed.
* gas/testsuite/gas/s390/zarch-z990.d: Refreshed.
* gas/testsuite/gas/s390/zarch-z990.s: Refreshed.
* gas/testsuite/gas/s390/zarch-zEC12.d: Refreshed.
* gas/testsuite/gas/s390/zarch-zEC12.s: Refreshed.
Diffstat (limited to 'opcodes')
-rw-r--r-- | opcodes/ChangeLog | 6 | ||||
-rw-r--r-- | opcodes/s390-mkopc.c | 2 | ||||
-rw-r--r-- | opcodes/s390-opc.c | 6 | ||||
-rw-r--r-- | opcodes/s390-opc.txt | 21 |
4 files changed, 32 insertions, 3 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 7684c66..0e148ad 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,9 @@ +2012-10-26 Andreas Krebbel <Andreas.Krebbel@de.ibm.com> + + * s390-mkopc.c: Accept empty lines in s390-opc.txt. + * s390-opc.c: Add M_20OPT field. New instruction formats RRF_RURR2 and RRF_RMRR. + * s390-opc.txt: Add new instructions. New instruction type for lptea. + 2012-10-26 Christian Groessler <chris@groessler.org> * z8kgen.c (struct op): Fix encoding for translate opcodes (trdb, diff --git a/opcodes/s390-mkopc.c b/opcodes/s390-mkopc.c index a1f0a12..c2c98de 100644 --- a/opcodes/s390-mkopc.c +++ b/opcodes/s390-mkopc.c @@ -343,7 +343,7 @@ main (void) int mode_bits; char *str; - if (currentLine[0] == '#') + if (currentLine[0] == '#' || currentLine[0] == '\n') continue; memset (opcode, 0, 8); if (sscanf (currentLine, "%15s %15s %15s \"%79[^\"]\" %15s %15s", diff --git a/opcodes/s390-opc.c b/opcodes/s390-opc.c index f421abe..0ae5603 100644 --- a/opcodes/s390-opc.c +++ b/opcodes/s390-opc.c @@ -230,6 +230,8 @@ const struct s390_operand s390_operands[] = #define M_16OPT 73 /* 4 bit optional mask starting at 16 */ { 4, 16, S390_OPERAND_OPTIONAL }, +#define M_20OPT 74 /* 4 bit optional mask starting at 20 */ + { 4, 20, S390_OPERAND_OPTIONAL }, }; @@ -342,8 +344,10 @@ const struct s390_operand s390_operands[] = #define INSTR_RRF_FUFF2 4, { F_24,F_28,F_16,U4_20,0,0 } /* e.g. adtra */ #define INSTR_RRF_FEUFEFE2 4, { FE_24,FE_28,FE_16,U4_20,0,0 } /* e.g. axtra */ #define INSTR_RRF_RURR 4, { R_24,R_28,R_16,U4_20,0,0 } /* e.g. .insn */ +#define INSTR_RRF_RURR2 4, { R_24,R_16,R_28,U4_20,0,0 } /* e.g. lptea */ #define INSTR_RRF_R0RR 4, { R_24,R_16,R_28,0,0,0 } /* e.g. idte */ #define INSTR_RRF_R0RR2 4, { R_24,R_28,R_16,0,0,0 } /* e.g. ark */ +#define INSTR_RRF_RMRR 4, { R_24,R_16,R_28,M_20OPT,0,0 } /* e.g. crdte */ #define INSTR_RRF_U0FF 4, { F_24,U4_16,F_28,0,0,0 } /* e.g. fixr */ #define INSTR_RRF_U0FEFE 4, { FE_24,U4_16,FE_28,0,0,0 } /* e.g. fixbr */ #define INSTR_RRF_U0RF 4, { R_24,U4_16,F_28,0,0,0 } /* e.g. cfebr */ @@ -500,8 +504,10 @@ const struct s390_operand s390_operands[] = #define MASK_RRF_FUFF2 { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } #define MASK_RRF_FEUFEFE2 { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } #define MASK_RRF_RURR { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RRF_RURR2 { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } #define MASK_RRF_R0RR { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } #define MASK_RRF_R0RR2 { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RRF_RMRR { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } #define MASK_RRF_U0FF { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } #define MASK_RRF_U0FEFE { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } #define MASK_RRF_U0RF { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } diff --git a/opcodes/s390-opc.txt b/opcodes/s390-opc.txt index 5946a05..cf9f079 100644 --- a/opcodes/s390-opc.txt +++ b/opcodes/s390-opc.txt @@ -715,6 +715,11 @@ b92f kmc RRE_RR "cipher message with chaining" z990 esa,zarch b93e kimd RRE_RR "compute intermediate message digest" z990 esa,zarch b93f klmd RRE_RR "compute last message digest" z990 esa,zarch b91e kmac RRE_RR "compute message authentication code" z990 esa,zarch +b99a epair RRE_R0 "extract primary ASN and instance" z990 esa,zarch +b99b esair RRE_R0 "extract secondary ASN and instance" z990 esa,zarch +b99e pti RRE_RR "program transfer with instance" z990 esa,zarch +b99f ssair RRE_R0 "set secondary ASN with instance" z990 esa,zarch + # z9-109 extended immediate instructions c209 afi RIL_RI "add immediate 32" z9-109 zarch c208 agfi RIL_RI "add immediate 64<32" z9-109 zarch @@ -759,7 +764,7 @@ b27c stckf S_RD "store clock fast" z9-109 zarch # z9-109 move with optional specifications instruction c800 mvcos SSF_RRDRD "move with optional specifications" z9-109 zarch # z9-109 load page-table-entry address instruction -b9aa lptea RRF_RURR "load page-table-entry address" z9-109 zarch +b9aa lptea RRF_RURR2 "load page-table-entry address" z9-109 zarch # z9-109 conditional sske facility, sske instruction entered twice b22b sske RRF_M0RR "set storage key extended" z9-109 zarch # z9-109 etf2-enhancement facility, instructions entered twice @@ -857,6 +862,7 @@ ed0000000059 tdgxt RXE_FERRD "test data group extended dfp" z9-ec zarch 010a pfpo E "perform floating point operation" z9-ec zarch c801 ectg SSF_RRDRD "extract cpu time" z9-ec zarch c802 csst SSF_RRDRD "compare and swap and store" z9-ec zarch + # The new instructions of the System z10 Enterprise Class eb000000006a asi SIY_IRD "add immediate (32<8)" z10 zarch eb000000007a agsi SIY_IRD "add immediate (64<8)" z10 zarch @@ -971,6 +977,9 @@ b286 qsi S_RD "query sampling information" z10 zarch b2e0 scctr RRE_RR "set cpu counter" z10 zarch b2e1 spctr RRE_RR "set peripheral counter" z10 zarch b280 lpp S_RD "load program parameter" z10 zarch +b928 pckmo RRE_00 "perform cryptographic key management operation" z10 zarch + +# The new instructions of the IBM zEnterprise z196 b9c8 ahhhr RRF_R0RR2 "add high high" z196 zarch b9d8 ahhlr RRF_R0RR2 "add high low" z196 zarch cc08 aih RIL_RI "add immediate high" z196 zarch @@ -992,7 +1001,7 @@ e300000000c4 lhh RXY_RRRD "load halfword high" z196 zarch e300000000ca lfh RXY_RRRD "load high" z196 zarch e300000000c2 llch RXY_RRRD "load logical character high" z196 zarch e300000000c6 llhh RXY_RRRD "load logical halfword high" z196 zarch -ec000000005D risbhg RIE_RRUUU "rotate then insert selected bits high" z196 zarch +ec000000005d risbhg RIE_RRUUU "rotate then insert selected bits high" z196 zarch ec0000000051 risblg RIE_RRUUU "rotate then insert selected bits low" z196 zarch e300000000c3 stch RXY_RRRD "store character high" z196 zarch e300000000c7 sthh RXY_RRRD "store halfword high" z196 zarch @@ -1104,6 +1113,12 @@ b3d8 mxtra RRF_FEUFEFE2 "multiply extended dfp with rounding mode" z196 zarch b3d3 sdtra RRF_FUFF2 "subtract long dfp with rounding mode" z196 zarch b3db sxtra RRF_FEUFEFE2 "subtract extended dfp with rounding mode" z196 zarch b2b8 srnmb S_RD "set 3 bit bfp rounding mode" z196 zarch +b92a kmf RRE_RR "cipher message with CFB" z196 zarch +b92b kmo RRE_RR "cipher message with OFB" z196 zarch +b92c pcc RRE_00 "perform cryptographic computation" z196 zarch +b92d kmctr RRF_R0RR2 "cipher message with counter" z196 zarch + +# The new instructions of the IBM zEnterprise EC12 b2ec etnd RRE_R0 "extract transaction nesting depth" zEC12 zarch e30000000025 ntstg RXY_RRRD "nontransactional store" zEC12 zarch b2fc tabort S_RD "transaction abort" zEC12 zarch @@ -1112,7 +1127,9 @@ e561 tbeginc SIL_RDU "constrained transaction begin" zEC12 zarch b2f8 tend S_00 "transaction end" zEC12 zarch c7 bpp SMI_U0RDP "branch prediction preload" zEC12 zarch c5 bprp MII_UPI "branch prediction relative preload" zEC12 zarch +b2e8 ppa RRF_U0RR "perform processor assist" zEC12 zarch b2fa niai IE_UU "next instruction access intent" zEC12 zarch +b98f crdte RRF_RMRR "compare and replace DAT table entry" zEC12 zarch e3000000009f lat RXY_RRRD "load and trap 32 bit" zEC12 zarch e30000000085 lgat RXY_RRRD "load and trap 64 bit" zEC12 zarch e300000000c8 lfhat RXY_RRRD "load high and trap" zEC12 zarch |