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| author | Michael Eager <eager@eagercon.com> | 2012-11-14 16:19:30 +0000 |
|---|---|---|
| committer | Michael Eager <eager@eagercon.com> | 2012-11-14 16:19:30 +0000 |
| commit | e692c2171ead6cdd096e625d6e8a4dd33d8bffe2 (patch) | |
| tree | 0647cee09b70142e87eec56bf9ac0a86ccc86671 /opcodes | |
| parent | aff68abbd7cfed062055bd2d97f464b304b920bc (diff) | |
| download | gdb-e692c2171ead6cdd096e625d6e8a4dd33d8bffe2.zip gdb-e692c2171ead6cdd096e625d6e8a4dd33d8bffe2.tar.gz gdb-e692c2171ead6cdd096e625d6e8a4dd33d8bffe2.tar.bz2 | |
Add the endian reversing versions of load/store instructions;
2012-11-14 Edgar E. Iglesias <edgar.iglesias@gmail.com>
* microblaze-opc.h: Increase MAX_OPCODES (op_code_struct): add lbur,
lhur, lwr, sbr, shr, swr
* microblaze-opcm.h (microblaze_instr): add lbur, lhur, lwr, sbr, shr,
swr
2012-11-14 David Holsgrove <david.holsgrove@xilinx.com>
* gas/microblaze/allinsn.exp: New file - test newly added opcodes
* gas/microblaze/allinsn.s: Likewise
* gas/microblaze/allinsn.d: Likewise
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/ChangeLog | 7 | ||||
| -rw-r--r-- | opcodes/microblaze-opc.h | 8 | ||||
| -rw-r--r-- | opcodes/microblaze-opcm.h | 3 |
3 files changed, 16 insertions, 2 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 466ae87..69248f8 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,10 @@ +2012-11-14 Edgar E. Iglesias <edgar.iglesias@gmail.com> + + * microblaze-opc.h: Increase MAX_OPCODES (op_code_struct): add lbur, + lhur, lwr, sbr, shr, swr + * microblaze-opcm.h (microblaze_instr): add lbur, lhur, lwr, sbr, shr, + swr + 2012-11-09 Nick Clifton <nickc@redhat.com> * configure.in: Add bfd_v850_rh850_arch. diff --git a/opcodes/microblaze-opc.h b/opcodes/microblaze-opc.h index 02ac83f..44c9d38 100644 --- a/opcodes/microblaze-opc.h +++ b/opcodes/microblaze-opc.h @@ -96,7 +96,7 @@ #define DELAY_SLOT 1 #define NO_DELAY_SLOT 0 -#define MAX_OPCODES 280 +#define MAX_OPCODES 284 struct op_code_struct { @@ -220,12 +220,18 @@ struct op_code_struct {"bgei", INST_TYPE_R1_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBCA00000, OPCODE_MASK_H1, bgei, branch_inst }, {"bgeid", INST_TYPE_R1_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBEA00000, OPCODE_MASK_H1, bgeid, branch_inst }, {"lbu", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC0000000, OPCODE_MASK_H4, lbu, memory_load_inst }, + {"lbur", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC0000200, OPCODE_MASK_H4, lbur, memory_load_inst }, {"lhu", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC4000000, OPCODE_MASK_H4, lhu, memory_load_inst }, + {"lhur", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC4000200, OPCODE_MASK_H4, lhur, memory_load_inst }, {"lw", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC8000000, OPCODE_MASK_H4, lw, memory_load_inst }, + {"lwr", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC8000200, OPCODE_MASK_H4, lwr, memory_load_inst }, {"lwx", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC8000400, OPCODE_MASK_H4, lwx, memory_load_inst }, {"sb", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD0000000, OPCODE_MASK_H4, sb, memory_store_inst }, + {"sbr", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD0000200, OPCODE_MASK_H4, sbr, memory_store_inst }, {"sh", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD4000000, OPCODE_MASK_H4, sh, memory_store_inst }, + {"shr", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD4000200, OPCODE_MASK_H4, shr, memory_store_inst }, {"sw", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD8000000, OPCODE_MASK_H4, sw, memory_store_inst }, + {"swr", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD8000200, OPCODE_MASK_H4, swr, memory_store_inst }, {"swx", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD8000400, OPCODE_MASK_H4, swx, memory_store_inst }, {"lbui", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xE0000000, OPCODE_MASK_H, lbui, memory_load_inst }, {"lhui", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xE4000000, OPCODE_MASK_H, lhui, memory_load_inst }, diff --git a/opcodes/microblaze-opcm.h b/opcodes/microblaze-opcm.h index 10acacf..a3bec49 100644 --- a/opcodes/microblaze-opcm.h +++ b/opcodes/microblaze-opcm.h @@ -36,7 +36,8 @@ enum microblaze_instr bltd, ble, bled, bgt, bgtd, bge, bged, ori, andi, xori, andni, imm, rtsd, rtid, rtbd, rted, bri, brid, brlid, brai, braid, bralid, brki, beqi, beqid, bnei, bneid, blti, bltid, blei, bleid, bgti, - bgtid, bgei, bgeid, lbu, lhu, lw, lwx, sb, sh, sw, swx, lbui, lhui, lwi, + bgtid, bgei, bgeid, lbu, lbur, lhu, lhur, lw, lwr, lwx, sb, sbr, sh, + shr, sw, swr, swx, lbui, lhui, lwi, sbi, shi, swi, msrset, msrclr, tuqula, fadd, frsub, fmul, fdiv, fcmp_lt, fcmp_eq, fcmp_le, fcmp_gt, fcmp_ne, fcmp_ge, fcmp_un, flt, fint, fsqrt, |