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| author | Michael Eager <eager@eagercon.com> | 2012-11-21 17:34:14 +0000 |
|---|---|---|
| committer | Michael Eager <eager@eagercon.com> | 2012-11-21 17:34:14 +0000 |
| commit | 0db4b3260cfc1818dba17ee53bb8e6ca6fdefecc (patch) | |
| tree | ebab98525dfab07eff0f4c02b90b40d3770ca3ee /opcodes | |
| parent | e0f33b1fbf3b88882abd0d4136b8d1307e351c9d (diff) | |
| download | gdb-0db4b3260cfc1818dba17ee53bb8e6ca6fdefecc.zip gdb-0db4b3260cfc1818dba17ee53bb8e6ca6fdefecc.tar.gz gdb-0db4b3260cfc1818dba17ee53bb8e6ca6fdefecc.tar.bz2 | |
Add stack high register and stack low register for MicroBlaze
hardware assisted stack protection, stores stack low / stack high limits
for detecting stack overflow / underflow
binutils/opcodes
* microblaze-opcm.h: Add REG_SLR_MASK, REG_SHR_MASK, REG_SHR and REG_SLR
* microblaze-dis.c (get_field_special): Handle REG_SLR_MASK and REG_SHR_MASK
binutils/gas
* config/tc-microblaze.c (parse_reg): Parse REG_SLR, REG_SHR
binutils/gas
* gas/microblaze/allinsn.s: Test use of SHR, SLR
* gas/microblaze/allinsn.d: Likewise
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/ChangeLog | 5 | ||||
| -rw-r--r-- | opcodes/microblaze-dis.c | 6 | ||||
| -rw-r--r-- | opcodes/microblaze-opcm.h | 4 |
3 files changed, 15 insertions, 0 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 2540f4d..e5d08b0 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,8 @@ +2012-11-21 Edgar E. Iglesias <edgar.iglesias@gmail.com> + + * microblaze-opcm.h: Add REG_SLR_MASK, REG_SHR_MASK, REG_SHR and REG_SLR + * microblaze-dis.c (get_field_special): Handle REG_SLR_MASK and REG_SHR_MASK + 2012-11-20 Kirill Yukhin <kirill.yukhin@intel.com> H.J. Lu <hongjiu.lu@intel.com> diff --git a/opcodes/microblaze-dis.c b/opcodes/microblaze-dis.c index e204e36..7e3a546 100644 --- a/opcodes/microblaze-dis.c +++ b/opcodes/microblaze-dis.c @@ -139,6 +139,12 @@ get_field_special (long instr, struct op_code_struct * op) case REG_TLBSX_MASK : strcpy (spr, "tlbsx"); break; + case REG_SHR_MASK : + strcpy (spr, "shr"); + break; + case REG_SLR_MASK : + strcpy (spr, "slr"); + break; default : if (((((instr & IMM_MASK) >> IMM_LOW) ^ op->immval_mask) & 0xE000) == REG_PVR_MASK) diff --git a/opcodes/microblaze-opcm.h b/opcodes/microblaze-opcm.h index 867263e..a2a42d0 100644 --- a/opcodes/microblaze-opcm.h +++ b/opcodes/microblaze-opcm.h @@ -79,6 +79,8 @@ enum microblaze_instr_type #define REG_BTR_MASK 0x800b #define REG_EDR_MASK 0x800d #define REG_PVR_MASK 0xa000 +#define REG_SLR_MASK 0x8800 +#define REG_SHR_MASK 0x8802 #define REG_PID_MASK 0x9000 #define REG_ZPR_MASK 0x9001 @@ -100,6 +102,8 @@ enum microblaze_instr_type #define REG_FSR 39 /* FPU Status reg. */ #define REG_BTR 43 /* Branch Target reg. */ #define REG_EDR 45 /* Exception reg. */ +#define REG_SHR 50 /* Stack High reg. */ +#define REG_SLR 51 /* Stack Low reg. */ #define REG_PVR 40960 /* Program Verification reg. */ #define REG_PID 36864 /* MMU: Process ID reg. */ |